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Enhancement of a Nanoscale Novel Esaki Tunneling Diode Source TFET (ETDS-TFET) for Low-Voltage Operations

  • Mohammad K. Anvarifard
  • Ali A. Orouji
Original Paper
  • 5 Downloads

Abstract

This paper presents a novel nanoscale tunnel FET consisting of an Esaki tunneling diode in the source region. A unique part of the source region is replaced by a heavily doped N-type silicon material establishing a tunneling diode inside the source region. Also, the gate metal is deliberately extended into the source region in order to more couple the created tunneling diode inside the source region. In the result of this new configuration, the band energy bending occurs inside the source region and also the potential barrier will be modified in the channel region thus increasing the ratio of ION to IOFF (ION/IOFF) and reducing the leakage current and ambipolar current for the proposed structure. The proposed structure has been compared with the conventional TFET and PNPN-TFET structure in terms of the ION/IOFF, Leakage current, ambipolar current, drain-source conductance, short channel effects, source-drain capacitance and minimum noise figure showing a performance superiority with respect to other structures under the study.

Keywords

Tunnel FET Esaki tunneling diode Band energy Potential barrier 

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References

  1. 1.
    Colinge JP (2004) Silicon-on-insulator technology: materials to VLSI3rd edn. Kluwer Academic Publishers, LondonCrossRefGoogle Scholar
  2. 2.
    Arnold E (1994) Silicon-on-insulator devices for high voltage and power IC applications. J Electro Chem Soc 141(7):1983–1988.  https://doi.org/10.1149/1.2055040 CrossRefGoogle Scholar
  3. 3.
    Cristoloveanu S (2011) Trends in SOI technology: hot and green. J Korean Phys Soc 58(5):1461–1467.  https://doi.org/10.3938/jkps.58.1461 CrossRefGoogle Scholar
  4. 4.
    Saremi M, Ebrahimi B, Afzali-Kusha A, Mohammadi S (2011) A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement. Microelectron Eng 51(12):2069–2076.  https://doi.org/10.1016/j.microrel.2011.07.084 CrossRefGoogle Scholar
  5. 5.
    Jamali Mahabadia SE, Rajabi S, Loiacono J (2015) A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self-heating effect enhancement. Superlattice Microst 85:872–879.  https://doi.org/10.1016/j.spmi.2015.07.011 CrossRefGoogle Scholar
  6. 6.
    Moghadam HA, Orouji AA, Dideban A (2011) A novel 4H–SiC SOI-MESFET with a modified breakdown voltage mechanism for improving the electrical performance. Semicond Sci Technol 27(1):015001.  https://doi.org/10.1088/0268-1242/27/1/015001 CrossRefGoogle Scholar
  7. 7.
    Anvarifard MK (2016) Successfully controlled potential distribution in a novel high-voltage and high-frequency SOI MESFET. IEEE Trans Device Mater Reliab 16(4):631–637.  https://doi.org/10.1109/TDMR.2016.2618850 CrossRefGoogle Scholar
  8. 8.
    Zareiee M, Orouji AA (2017) Superior electrical characteristics of novel nanoscale MOSFET with embedded tunnel diode. Superlattice Microst 101:57–67.  https://doi.org/10.1016/j.spmi.2016.11.022 CrossRefGoogle Scholar
  9. 9.
    Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110.  https://doi.org/10.1109/JPROC.2010.2070470 CrossRefGoogle Scholar
  10. 10.
    Barah D, Singh AK, Bhowmick B (2018) TFET on selective buried oxide (SELBOX) substrate with improved ION/IOFF ratio and reduced Ambipolar current. Silicon:1–9.  https://doi.org/10.1007/s1263
  11. 11.
    Koswatta SO, Lundstrom MS, Nikonov DE (2009) Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans Electron Devices 56(3):456–465.  https://doi.org/10.1109/TED.2008.2011934 CrossRefGoogle Scholar
  12. 12.
    Kumar MJ, Janardhanan S (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE Trans Electron Devices 60(10):3285–3290.  https://doi.org/10.1109/TED.2013.2276888 CrossRefGoogle Scholar
  13. 13.
    Saurabh S, Kumar MJ (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58(2):404–410.  https://doi.org/10.1109/TED.2010.2093142 CrossRefGoogle Scholar
  14. 14.
    Molaei R, Saremi M (2018) A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications. J Electron Mater 47(2):1091–1098.  https://doi.org/10.1007/s11664-017-5823-z CrossRefGoogle Scholar
  15. 15.
    Vishnoi R, Kumar MJ (2014) A pseudo-2-D-analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans Electron Devices 61(7):2264–2270.  https://doi.org/10.1109/TED.2014.2321977 CrossRefGoogle Scholar
  16. 16.
    Molaei R, Saremi M, Vandenberghe WG (2017) A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance. IEEE Trans Electron Devices 64(11):4752–4758.  https://doi.org/10.1109/TED.2017.2755507 CrossRefGoogle Scholar
  17. 17.
    Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733.  https://doi.org/10.1109/TED.2007.899389 CrossRefGoogle Scholar
  18. 18.
    Basak S, Asthana PK, Goswami Y, Ghosh B (2015) Leakage current reduction in junctionless tunnel FET using a lightly doped source. Appl Phys A Mater Sci Process 118:527–1533.  https://doi.org/10.1007/s00339-014-8935-9 CrossRefGoogle Scholar
  19. 19.
    Jhaveri R, Nagavarapu V, Woo JCS (2011) Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans Electron Devices 58(1):80–86.  https://doi.org/10.1109/TED.2010.2089525 CrossRefGoogle Scholar
  20. 20.
    Hurkx GAM, Klaassen DBM, Knuvers MPG (1992) A new recombination model for device simulation including tunneling. IEEE Trans Electron Devices 39:331–338.  https://doi.org/10.1109/16.121690 CrossRefGoogle Scholar
  21. 21.
    (2015) ATLAS device simulation software. Silvaco, Santa Clara, https://www.silvaco.com.
  22. 22.
    Kedzierski J, Boyd D, Zhang Y, Steen M, Jamin FF, Benedict J, Ieong M, Haensch W (2003) Issues in NiSi-gated FDSOI device integration. In: IEDM Tech. Dig., pp 18.4.1–18.4.4.  https://doi.org/10.1109/IEDM.2003.1269317

Copyright information

© Springer Nature B.V. 2018

Authors and Affiliations

  1. 1.Department of Engineering Sciences, Faculty of Technology and Engineering, East of GuilanUniversity of GuilanRudsar-VajargahIran
  2. 2.Electrical Engineering DepartmentSemnan UniversitySemnanIran

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