, Volume 11, Issue 1, pp 549–556 | Cite as

Analysis of Encoder and Decoder by using Multiple Valued (MV) Hybrid SETMOS

  • Jyoti R. ChaudhariEmail author
  • D. K. Gautam
Original Paper


In Integrated Circuit (IC) Technology practical circuit application of single electron devices is impossible due to it poor driving capability according to this point it is essential to accept implementation of new methodology such as hybridization of single electron transistor (SET) and complementary metal oxide semiconductor (CMOS) device interface circuit. This hybrid SETMOS is operated in room temperature. Further with the help of science and technology, it is easy to communicate with people all over the world, within a minute by sharing large amount of information through messages and email. So it is essential to study the fastest communication in analog and digital media. High speed computing technological faces lots of problems so it is essential to think different pathway to improve communication performance in the future. Generally basic communication system includes encoder and decoder to convert and convey the information in different pathway. In this paper we proposed basic building blocks of communication system using Multiple Valued logic (MVL). Herein binary to quaternary encoder is implemented by using NAND and NOR gate. Quaternary to binary decoder is proposed by using literal and universal literal gate. MIB model of SET is calibrated with conventional BSIM 4.6.1 MOSFET 45nm model. All circuits are simulated and validated in T-spice pro environment. The proposed NAND and NOR gate consumes 2050nw and 42ps delay while literal and universal literal gate consume 1050nw and 41ps delay in comparison to CMOS counterparts.


Multiple-valued logic MIB SETMOS Literal/universal literal gate NAND NOR 


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© Springer Science+Business Media B.V., part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics Engineering and TechnologyNorth Maharashtra UniversityJalgaonIndia

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