Parallel arrays of Schottky barrier nanowire field effect transistors: Nanoscopic effects for macroscopic current output
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We present novel Schottky barrier field effect transistors consisting of a parallel array of bottom-up grown silicon nanowires that are able to deliver high current outputs. Axial silicidation of the nanowires is used to create defined Schottky junctions leading to on/off current ratios of up to 106. The device concept leverages the unique transport properties of nanoscale junctions to boost device performance for macroscopic applications. Using parallel arrays, on-currents of over 500 μA at a source-drain voltage of 0.5 V can be achieved. The transconductance is thus increased significantly while maintaining the transfer characteristics of single nanowire devices. By incorporating several hundred nanowires into the parallel array, the yield of functioning transistors is dramatically increased and deviceto-device variability is reduced compared to single devices. This new nanowirebased platform provides sufficient current output to be employed as a transducer for biosensors or a driving stage for organic light-emitting diodes (LEDs), while the bottom-up nature of the fabrication procedure means it can provide building blocks for novel printable electronic devices.
Keywordssilicon nanowire effective Schottky barrier lowering parallel array electric field enhancement output current amplification
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- Weber, W. M.; Graham, A. P.; Duesberg, G. S.; Liebau, M.; Cheze, C.; Geelhaar, L.; Unger, E.; Pamler, W.; Hoenlein, W.; Riechert, H.; et al. Non-linear gate length dependence of on-current in Si-nanowire FETs. In Proceedings of the 36th European Solid-State Device Research Conference (ESSDERC), 2006.Google Scholar
- Park, H.; Park, S.; Hong Shick, M.; Seonghoon, J. Investigation of noise in silicon nanowire transistors through quantum simulations. In Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2008.Google Scholar
- Saurabh, M.; Mohata, D.; Ramakrishnan, K.; Jawar, S.; Aaron, V. L.; Ashkar, A.; Mayer, T. S.; Vijaykrishnan, N.; Schlom, D. G.; Liu, A. W. K.; et al. Experimental demonstration of 100 nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications. In Proceedings of IEEE International Conference on Electron Devices Meeting (IEDM), 2009.Google Scholar
- Bhuwalka, K. K.; Schulze, J.; Eisele, I. Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. In Proceedings of IEEE International Conference on Transactions on Electron Devices, 2005.Google Scholar
- Zhang, M.; Knoch, J.; Zhao, Q. T.; Lenk, S.; Breuer, U.; Mantl, S. Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs. In: Proceedings of European Solid-State Device Research Conference (ESSDERC), 2005, Grenoble, France.Google Scholar
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