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High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

  • Pengfei Lian (廉鹏飞)Email author
  • Bin Wu (吴 斌)
  • Han Wang (王 晗)
  • Yilin Pu (蒲钇霖)
  • Chengying Chen (陈铖颖)
Article
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Abstract

We propose a high performance 10-bit 100-MS/s (million samples per second) successive approximation register (SAR) analog-to-digital converter (ADC) with mismatch correction latch and improved comparator clock. Using a high-low supply voltage technology, the bias output impedance of the preamplifier of the comparator is increased. Therefore, the common mode rejection ratio (CMRR) of the comparator is improved, and further diminishing the signal-dependent offset caused by the input common-mode voltage variation. A digital-to-analog converter (DAC) control signal correction latch is proposed to correct the control signal error resulted from process mismatch. The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free dynamic range (SFDR) of the ADC is improved by 2 dB with this correction latch. To ensure sufficient high bit switching time of the DAC and sufficient low bit comparison time of the comparator, a data selector used in the comparator clock is presented. The optimized time distribution improves the performance of the SAR ADC. This prototype was fabricated using a one-poly-eight-metal (1P8M) 55 nm complementary metal oxide semiconductor (CMOS) technology. With measured results at 1.3V/1.5V supply and 100-MS/s, the ADC achieves a signalto- noise and distortion ratio (SNDR) of 59.4 dB and consumes 2.1mW, resulting in a figure of merit (FOM) of 31 fJ/conversion-step. In addition, the active area of the ADC is 0.018 8mm2.

Key words

analog-to-digital converter successive approximation register high-low supply voltage mismatch correction data selector 

CLC number

TN 43 

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References

  1. [1]
    YUAN C, LAM Y. Low-energy and area-efficient trilevel switching scheme for SAR ADC [J]. Electronics Letters, 2012, 48(9): 482–483.CrossRefGoogle Scholar
  2. [2]
    ZHU Z M, XIAO Y, SONG X L. VCM-based monotonic capacitor switching scheme for SAR ADC [J]. Electronics Letters, 2013, 49(5): 327–329.CrossRefGoogle Scholar
  3. [3]
    ZHU Y, CHAN C H, CHIO U F, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2010, 45(6): 1111–1121.CrossRefGoogle Scholar
  4. [4]
    RAHIMI E, YAVARI M. Energy-efficient highaccuracy switching method for SAR ADCs [J]. Electronics Letters, 2014, 50(7): 499–501.CrossRefGoogle Scholar
  5. [5]
    XIE L B, SU J, LIU J X, et al. Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs [J]. Electronics Letters, 2015, 51(6): 460–462.CrossRefGoogle Scholar
  6. [6]
    CAO Z H, YAN S L, LI Y C. A 32mW 1.25 GS/s 6 b 2 b/step SAR ADC in 0.13 µm CMOS [C]//International Solid-State Circuits Conference: Digest of Techical Papers. San Francisco, CA, USA: IEEE, 2008: 542–543.Google Scholar
  7. [7]
    CRANINCKX J, VAN DER PLAS G. A 65 fJ/ conversion-step 0-to-50MS/s 0-to-0.7mW 9 b chargesharing SAR ADC in 90 nm digital CMOS [C]// International Solid-State Circuits Conference: Digest of Technology Papers. San Francisco, CA, USA: IEEE, 2007: 246–247.Google Scholar
  8. [8]
    GIANNINI V, NUZZO P, CHIRONI V, et al. An 820 µW 9b 40MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS [C]// International Solid-State Circuits Conference: Digest of Technology Papers. San Francisco, CA, USA: IEEE, 2008: 238–239.Google Scholar
  9. [9]
    LIU C C, CHANG S J, HUANG G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure [J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 731–740.CrossRefGoogle Scholar
  10. [10]
    LIN J Y, HUANG H Y, HSIEH C C, et al. A 0.05mm2 0.6V 500 kS/s 14.3 fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager [C]// IEEE Asian Solid State Circuits Conference. Kobe, Japan: IEEE, 2012: 165–168.Google Scholar
  11. [11]
    ZHU Z M, XIAO Y, XU L F, et al. An 8/10 bit 200/100 MS/s configurable asynchronous SAR ADC [J]. Analog Integrated Circuits and Signal Processing, 2013, 77(2): 249–255.CrossRefGoogle Scholar

Copyright information

© Shanghai Jiao Tong University and Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Pengfei Lian (廉鹏飞)
    • 1
    Email author
  • Bin Wu (吴 斌)
    • 2
  • Han Wang (王 晗)
    • 3
  • Yilin Pu (蒲钇霖)
    • 2
  • Chengying Chen (陈铖颖)
    • 4
  1. 1.No. 808 Institute of Shanghai Academy of Spaceflight TechnologyShanghaiChina
  2. 2.Institute of MicroelectronicsChinese Academy of SciencesBeijingChina
  3. 3.Analog and RF DepartmentBeijing Casemic Electronic Technologies Co., Ltd.BeijingChina
  4. 4.School of MicroelectronicsXiamen University of TechnologyXiamenChina

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