, 44:137 | Cite as

A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture

  • Kalpana G BhatEmail author
  • T Laxminidhi
  • M S Bhat


A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 μW achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits.


Analog to digital converter (ADC) successive approximation register (SAR) parasitic insensitive programmable resolution low power charge recycling 2-bit per cycle nonbinary 



Authors would like to thank Ministry of Electronics and Information Technology (MeitY), Government of India, for providing EDA tools through SMDP-VLSI Project.


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Copyright information

© Indian Academy of Sciences 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of Technology KarnatakaSurathkalIndia

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