Advertisement

Pramana

, 92:2 | Cite as

Analytical modelling of electrical parameters and the analogue performance of cylindrical gate-all-around FinFET

  • Rajashree DasEmail author
  • Srimanta Baishya
Article
  • 35 Downloads

Abstract

This paper presents the cylindrical gate-all-around (GAA) silicon on insulator (SOI) FinFET, which not only eliminates the corner effect but also shows high on-drain current (\(I_{\mathrm{ON}}\)) (\(\sim \!\!10^{-2}~\mathrm{A}\)), low leakage current (\(I_{\mathrm{OFF}}\)) (\( \sim \!\!10^{-10}~\mathrm{A}\)), high \(I_{\mathrm{ON}}\) \(/\) \(I_{\mathrm{OFF}}\) (\(10^{8}>10^{6}\)) and reduced subthreshold swing (SS) (64.55 mV / dec, which is nearest to the Boltzmann limit of 60 mV / dec). To have a better understanding of the working principles, analytical modelling of electrical parameters such as surface potential, threshold voltage, drain current and SS has been carried out by solving two-dimensional Poisson’s equation using superposition principle. The behaviour of threshold voltage, drain current and SS has been investigated for different dimensional and electrical parameters such as channel lengths, channel radius, gate work functions, dielectric constants, drain-to-source voltages and channel concentrations. The physics-based models have been cross-examined with extracted three-dimensional TCAD simulation results. The modelled values show good agreement with the simulated data. Moreover, analogue performances such as transconductance, output conductance, intrinsic gain and gate capacitance for different channel lengths and radii of the presented device are also studied.

Keywords

Analytical modelling drain current cylindrical gate-all-around subthreshold swing threshold voltage analogue parameters 

PACS Nos

70 73 

References

  1. 1.
    D Hisamoto, W-C Lee, J Kedzierski, H Takeuchi, K Asano, C Kuo, E Anderson, T-J King, J Bokor and C Hu, IEEE Trans. Electron Devices 47, 2320 (2000)ADSCrossRefGoogle Scholar
  2. 2.
    A Datta, A Goel, R T Cakici, H Mahmoodi, D Lekshmanan and K Roy, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26, 1957 (2007)CrossRefGoogle Scholar
  3. 3.
    S L Tripathi, R Mishra and R A Mishra, 2nd International Conference on Power, Control and Embedded Systems (2012) Vol. 1, p. 1Google Scholar
  4. 4.
    G Pei, J Kedzierski, P Oldiges, M Ieong and E C C Kan, IEEE Trans. Electron Devices 49, 1411 (2002)ADSCrossRefGoogle Scholar
  5. 5.
    D Bhattacharya and N K Jha, Adv. Electron. 2014, 1 (2014)CrossRefGoogle Scholar
  6. 6.
    B Yu, L Chang, S Ahmed, H Wang, S Bell, C Y Yang, C Tabery, C Ho, Q Xiang, T-J King, J Bokor, C Hu, M-R Lin and D Kyser, International Electron Devices Meeting (2002) Vol. 251Google Scholar
  7. 7.
    M A Pavanello, J A Martino, E Simoen, R Rooyackers, N Collaert and C Claeys, Solid State Electron. 51, 285 (2007)ADSCrossRefGoogle Scholar
  8. 8.
    T Rudenko, V Kilchytska, N Collaert, M Jurczak, A Nazarov and D Flandre, IEEE Trans. Electron Devices 55, 3532 (2008)ADSCrossRefGoogle Scholar
  9. 9.
    R Das, R Goswami and S Baishya, Superlatt. Microstruct. 91, 51 (2016)ADSCrossRefGoogle Scholar
  10. 10.
    V Narendar and R A Mishra, Superlatt. Microstruct. 85, 357 (2015)ADSCrossRefGoogle Scholar
  11. 11.
    M D Ko, C W Sohn, C K Baek and Y H Jeong, IEEE Trans. Electron Devices 60, 2721 (2013)ADSCrossRefGoogle Scholar
  12. 12.
    K Wu, W W Ding and M H Chiang, International Conference on Simulation of Semiconductor Process and Devices (2013) Vol. 143Google Scholar
  13. 13.
    Y Li, H M Chou and J W Lee, IEEE Trans. Nanotechnol. 4, 510 (2005)ADSCrossRefGoogle Scholar
  14. 14.
    B Lakshmi and R Srinivasan, Int. J. Numer. Modell. 30, 1 (2016)Google Scholar
  15. 15.
    C Chang, J Lin, P Lin, H Hsu, C Chang, M Shih, S Tseng and M Lin, Int. J. Math. Comput. Phys. Electr. Comput. Eng. 7, 333 (2013)Google Scholar
  16. 16.
    A Burenkov and J Lorenz, 33rd Conference on European Solid-State Device Research (2003) Vol. 3Google Scholar
  17. 17.
    M Poljak, V Jovanovic and T Suligoj, Microelectron. Eng. 87, 192 (2010)CrossRefGoogle Scholar
  18. 18.
    M Stadele, R J Luyken, M Roosz, M Specht, W Rosner, L Dreeskornfeld, J Hartwich, F Hofmann, J Kretz, E Landgraf and L Risch, Proceedings of 34th European Solid-State Device Research Conference (2004) Vol. 165Google Scholar
  19. 19.
    M Bhole, A Kurude and S Pawar, Int. J. Eng. Sci. Res. Technol. 2, 2 (2013)Google Scholar
  20. 20.
    Sentaurus Device User, Synopsys, 2009 (2009)Google Scholar
  21. 21.
    K V Ramanan and R K Gupta, Electron. Lett. 7, 221 (1971)CrossRefGoogle Scholar
  22. 22.
    B Ray and S Mahapatra, IEEE Trans. Electron Devices 55, 2409 (2008)ADSCrossRefGoogle Scholar
  23. 23.
    H A Hamid, B Iñíguez and J R Guitart, IEEE Trans. Electron Devices 54, 572 (2007)ADSCrossRefGoogle Scholar
  24. 24.
    Q Chen, B Agrawal and J D Meindl, IEEE Trans. Electron Devices 49, 1086 (2002)ADSCrossRefGoogle Scholar
  25. 25.
    Q Chen, E M Harrell and J D Meindl, IEEE Trans. Electron Devices 50, 1631 (2003)ADSCrossRefGoogle Scholar
  26. 26.
    Y Chen and J Luo, Technical Proceedings, 2001 International Conference on Modeling and Simulation of Microsystems (2001) Vol. 1, p. 546Google Scholar
  27. 27.
    A Kranti, S Haldar and R S Gupta, Microelectron. J. 32, 305 (2001)CrossRefGoogle Scholar
  28. 28.
    Y Tsividis and C McAndrew, Operation and modeling of the MOS transistor, 3rd edn (McGraw-Hill, NewYork, 2011) p. 212Google Scholar
  29. 29.
    Y Pratap, P Ghosh, S Haldar, R S Gupta and M Gupta, Microelectron. J. 45, 408 (2014)CrossRefGoogle Scholar
  30. 30.
    J Widiez, F Dauge, T Poiroux, B Previtali, M Mouis and S Deleonibus, 2004 IEEE International SOI Conference (2004) Vol. 185Google Scholar
  31. 31.
    P Dutta, B Syamal, K Koley, A Dutta and C K Sarkar, Pramana – J. Phys. 89:33 (2017)ADSCrossRefGoogle Scholar
  32. 32.
    B Yang, K D Buddharaju, S H G Teo, N Singh, G Q Lo and D L Kwong, IEEE Electron Devices Lett. 29, 791 (2008)ADSCrossRefGoogle Scholar
  33. 33.
    B Jena, K P Pradhan, S Dash, G P Mishra, P K Sahu and S K Mohapatra, Adv. Natural Sci.: Nanosci. Nanotechnol. 6, 035010 (2015)ADSGoogle Scholar

Copyright information

© Indian Academy of Sciences 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of TechnologySilcharIndia

Personalised recommendations