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Silicon carbide die sintering layer: manufacturing process optimization and modeling

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Abstract

The massive development of Hybrid and Electrical Vehicles is strongly impacting the semiconductor industry demanding for highly reliable Power Electronic components. These challenges mainly originate from Silicon Carbide MOSFET’s superior properties allowing high power, high temperature capability, fast switching transients and high electric field operations. All these features can be obtained in a significant reduced chip area. In order to benefit from the disrupting advantages of these wide band gap semiconductor based power devices, a strong focus on silver sintering, as one of the most promising die attach technologies, is needed to withstand these challenging requirements. The aim of this work is to develop an integrated methodology, numerical and experimental, to assess the Ag sintering die attach process for a SiC power MOSFET. Different process parameters have been benchmarked by means of physical analyses, performed at time zero and also after liquid-to-liquid thermal shock aging test. The sintering flakes densification process has been reproduced by Finite Element Analysis and the obtained morphological texture has been used for extracting the mechanical properties of the layer as a function of the thermo-compression process itself. A simulation method, based on the evaluation of the inelastic strain accounted per cycle has been used for matching the experimental results according to an aging model. Furthermore, it has been predicted the silver sintering performances considering an active temperature cycle. The proposed methodology has supported the optimization of silver sintering parameters and has calculated the reliability performances of the silver sintering joint due to costumer-like active temperature cycle. Negligible sintering degradation has been carried out with a predicted number of cycles over two millions, suggesting die attach failure is not a relevant reliability bottleneck.

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Abbreviations

AMB:

Active metal brazed

CAD:

Computer aided design

EoL:

End of life

FEA:

Finite element analysis

FIB:

Focus ion beam

MOSFET:

Metal-oxide-semiconductor field-effect transistor

PFPE:

Perfluoropolyether

SAM:

Scanning acoustic microscopy

SEM:

Scanning electron microscopy

\(V_F\) :

Body diode forward voltage

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Acknowledgements

The authors thank Marco Torrisi and Sebastiano Russo (STMicroelectronics) for the support in the experimental and reliability activities.

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Authors and Affiliations

  1. ADG R&D, STMicroelectronics, Stradale Primosole, 50, 95121, Catania, Italy

    Michele Calabretta & Alessandro Sitta

  2. Dipartimento di Ingegneria Elettrica, Elettronica ed Informatica (DIEEI), Università degli Studi di Catania, Viale Andrea Doria, 6, 95125, Catania, Italy

    Gaetano Sequenzia

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  1. Michele Calabretta
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  2. Alessandro Sitta
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  3. Gaetano Sequenzia
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Correspondence to Michele Calabretta.

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This paper belongs to a research path funded by Regione Sicilia (Azione 1.2.1_03 del PO FESR SICILIA 2014-2020-Progetto PON03PE_00206_1 AMELIE“Advanced framework for Manufacturing Engineering and product Lifecycle Enhancement.”CUP G76I20000060007)

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Calabretta, M., Sitta, A. & Sequenzia, G. Silicon carbide die sintering layer: manufacturing process optimization and modeling. Int J Interact Des Manuf 16, 167–176 (2022). https://doi.org/10.1007/s12008-021-00815-8

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  • DOI: https://doi.org/10.1007/s12008-021-00815-8

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