A reconfigurable computing architecture for 5G communication

一种面向5G 通信的可重构计算架构

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5G baseband signal processing places greater real-time and reliability requirements on hardware. Based on the architecture of the MaPU, a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing. A dedicated instruction set for 5G baseband signal processing is proposed. The corresponding functional units are designed for reuse of hardware resources. A redirected register file is proposed to address latency and power consumption issues in internetwork. A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is low. The access mode of the data memory is extended, the performance is improved and the power consumption is reduced. The throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power consumption. The silicon area evaluated by layout is 5.8 mm2, which is 1/6 of the MaPU’s. The average power consumption is 0.7 W, which is 1/5 of the MaPU’s.


5G 基带信号处理对硬件提出了更高的实时性和可靠性要求。基于MaPU 的体系结构,根据5G 基带信号处理的特点,本文提出了一种可重构的计算体系结构。首先,提出了一种用于5G 基带信号 处理的专用指令集,并完成了相应的功能单元的硬件资源复用设计,然后,提出了重定向寄存器文件 来解决互联网络中的延迟和功耗问题。针对指令存储器的使用率低的情况,提出了二维码压缩方案。 并扩展了数据存储器的访问模式,使性能得到改善,功耗明显降低。本架构的5G 基带处理算法的吞 吐量比TMS320C6670 高出一到两个数量级,功耗更低。布局评估的硅面积为5.8 mm2,是MaPU 面 积的1/6。平均功耗为0.7 W,是MaPU 的1/5。

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  1. [1]

    ZIEGLER V, THEIMER T, SARTORI C, PRADE J, SPRECHER N, ALBAL K, BEDEKAR A. Architecture vision for the 5G era [C]// IEEE International Conference on Communications Workshops. IEEE, 2016: 51–56. DOI:

  2. [2]

    GONZALEZ-PLAZA A, MORENO J, VAL I, ARRIOLA A, RODRIGUEZ P M, JIMENEZ F, BRISO C. 5G communications in high speed and metropolitan railways [C]// European Conference on Antennas and Propagation. IEEE, 2017: 658–660. DOI:

  3. [3]

    DEHON A, WAWRZYNEK J. Reconfigurable computing:what, why, and implications for design automation [C]// Proc Design Automation Conference. 1999: 610–615. DOI:

  4. [4]

    FERREIRA M L, FERREIRA J C. Reconfigurable NC-OFDM processor for 5G communications [C]// International Conference on Embedded and Ubiquitous Computing. IEEE, 2015: 199–204. DOI:

  5. [5]

    WANG Dong-lin, XIE Shao-lin, ZHANG Zhi-wei, DU Xueliang, WAND Lei, LIU Zi-jun, LIN Xiao, HAO Jie, YIN Lei-zu, WANG Tao, YANG Yong-yong, LIN Chen, MA Hong Ma, PU Zhong-hua, DING Guang-xin, SUN Wen-qin, ZHOU Fa-biao, REN Wei-li, WANG Hui-juan Wang, ZHU Meng-chen, YANG Li-peng, XIAO Nuo-Zhou, CUI Qian Cui, WANG Xin-gang, GUO Ruo-shan Guo, WANG Xiaoqin. MaPU: A novel mathematical computing architecture [C]// IEEE International Symposium on High Performance Computer Architecture. IEEE, 2016: 457–468. DOI:

  6. [6]

    KANTEE D. CEVA Telegraphs 5G intent with XC12 [EB/OL]. [2019-4-21].

  7. [7]

    Texas Instruments. TMS320C6670 multicore fixed and floating-point system-on-chip [EB/OL]. [2019-4-21].

  8. [8]

    Cadence. Tensilica ConnX BBE Family of Performance Baseband DSPs [EB/OL]. [2019-4-21].

  9. [9]

    FENG Jing, LIU Zi-jun, MA Xiao-jun, GUO Yang, GUO Peng, WANG Dong-lin. A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration [C]// IEEE International Conference on Software Engineering and Service Science. IEEE, 2017: 567–570. DOI:

  10. [10]

    YANG Guo, GUO Yang, XIE Shao-lin, LIU Zi-jun, YANG Lei, WANG Dong-lin. Parallel polar encoding in 5G communication [C]// IEEE Symposium on Computers and Communications. IEEE, 2018. DOI:

  11. [11]

    LEROUX C, TAL I, VARDY A, GROSS W J. Hardware architectures for successive cancellation decoding of polar codes [C]// IEEE International Conference on Acoustics, Speech and Signal Processing. IEEE, 2011: 1665–1668. DOI:

  12. [12]

    CONG J, FAN Y, XU J. Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture [J]. ACM Transactions on Design Automation of Electronic Systems, 2006, 14(3): 824–833. DOI:

  13. [13]

    HUANG Y S, HONG Y J, HUANG J D. Communication synthesis for interconnect minimization targeting distributed register-file microarchitecture [J]. IEICE Transactions on Fundamentals of Electronics Communications & Computer Sciences, 2011, 94–A(4): 1151–1155. DOI:

  14. [14]

    HUANG J D, CHEN C I, HSU W L, LIN Y T, JOU J Y. Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay [C]// Proceedings of 2010 International Symposium on VLSI Design, Automation and Test. IEEE, 2010: 169–172. DOI:

  15. [15]

    GUO Yang, WANG Dong-lin, LIU Zi-jun, MENG Hong-yu. A distributed register file architecture based on dynamic scheduling for VLIW machine [C]// International Conference on Electronics Information and Emergency Communication. IEEE, 2018: 67–70. DOI:

  16. [16]

    JIN T, AHN M, YOO D, SUH D, LEE S. Nop compression scheme for high speed DSPs based on VLIW architecture [C]// IEEE International Conference on Consumer Electronics. IEEE, 2014: 304–305. DOI:

  17. [17]

    HELKALA J, VIITANEN T, KULTALA H, JÄÄSKELÄINEN P, BERG H. Variable length instruction compression on transport triggered architectures [C]// International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. IEEE, 2018: 149–155. DOI:

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Correspondence to Yang Guo 郭阳.

Additional information

Foundation item: Project(XDA-06010402) supported by the Strategic Priority Research Program of Chinese Academy of Sciences; Project (Y5S7061G51) supported by the Youth Innovation Promotion Association of Chinese Academy of Sciences

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Guo, Y., Liu, Z., Yang, L. et al. A reconfigurable computing architecture for 5G communication. J. Cent. South Univ. 26, 3315–3327 (2019) doi:10.1007/s11771-019-4255-8

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Key words

  • 5G communication
  • instruction set
  • register file
  • code compression
  • throughput
  • power consumption


  • 5G 通信
  • 指令集
  • 寄存器文件
  • 代码压缩
  • 吞吐率
  • 功耗