Journal of Electronics (China)

, Volume 26, Issue 3, pp 380–386 | Cite as

Reconfigurable RDMA communication framework of MULTI-DSP

Article
First Online:
Received:
Revised:
  • 24 Downloads

Abstract

The processing speed of the communication between nodes in a parallel processor has become the major bottleneck of the processor’s performance. RDMA (Remote Direct Memory Access) technology has drawn more attention recently due to its capability of transferring a larger amount of data, higher speed and reliability. 4DSP (4 Digital Signal Processing) module comprised of Tiger-SHARC201 chip is connected by LVDS (Low Voltage Differential Signal) circuits. This paper proposes a general and reconfigurable RDMA platform and its corresponding communication protocol with all the routes linked based on the zero copy. The protocol transfers message of DSP by interrupting of DMA and is applied on massive remote image impression, which reduces memory needs and working burden of CPU. The experiment results show this platform is efficient, flexible, and expandable of being integrated to a larger scale in the next development stages.

Key words

DSP (Digital Signal Processing) DMA (Direct Memory Access) LVDS (Low Voltage Differential Signal) Parallel processing Zero copy 

CLC index

TP391 
This is a preview of subscription content, log in to check access.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    T. Richter, W. Drescher, and F. Engel. A platform-based highly parallel digital signal processor. IEEE Custom Integrated Circuits Conference, San Diego, May 6–9, 2001, 305–308.Google Scholar
  2. [2]
    C. B. Cameron, R. N. Rodriguez, and N. Padgett. Fast optical ray tracing using multiple DSPs. IEEE Transactions on Instrumentation and Measurement, 55(2006)3, 801–808.CrossRefGoogle Scholar
  3. [3]
    D. Goldenberg, M. Kagan, R. Ravid, et al. Transparently achieving superior socket performance using zero copy socket direct protocol over 20 Gb/s infiniband links. IEEE International Conference on Cluster Computing, Boston, USA, September 27–30, 2005, 1–10. DOI: 10.1109/CLUSTR.2005.347027.Google Scholar
  4. [4]
    S. Liang, W. K. Yu, and D. K. Panda. High performance block I/O for global file system (GFS) with infiniband RDMA. International Conference on Parallel Processing, Columbus, USA, August 14–18, 2006, 391–398.Google Scholar
  5. [5]
    D. Dalessandro and P. A. Wyckoff. A performance analysis of the ammasso RDMA enabled ethernet adapter and its iWARP API. IEEE International Conference on Cluster Computing, Boston, USA, September 27–30, 2005, 1–7. DOI: 10.1109/CLUSTR. 2005.347028.Google Scholar
  6. [6]
    Analog Device. The ADSP-TS201 tigerSHARC processor hardware reference. [EB]. http://www.analog.com/UploadedFiles/Associated_Docs/396096833ts201_hwr.pdf, 2003.
  7. [7]
    D. S. Peranconi and H. G. G. Cavalheiro. Using active messages to explore high performance in clusters of computers. Proceedings of the 25th International Conference of the Chilean Computer Science Society, Valdivia, Chile, November 7–12, 2005, 1–8.Google Scholar
  8. [8]
    E. P. Markatos and M. G. H. Katevenis. User-level DMA without operating system kernel modification. Third International Symposium on High-Performance Computer Architecture, San Antonio, February 1–5, 1997, 322–331.Google Scholar
  9. [9]
    C. Mathis, B. Rinner, and M. Schmid. A new approach to model communication for mapping and scheduling DSP-applications. IEEE International Conference on Acoustics Speech and Signal Processing, Istanbul, Turkey, June 5–9 2000, 3354–3357.Google Scholar

Copyright information

© Science Press, Institute of Electronics, CAS and Springer-Verlag GmbH 2009

Authors and Affiliations

  1. 1.61081 Army PLABeijingChina
  2. 2.School of Computer Science and EngineeringBeihang UniversityBeijingChina
  3. 3.The Fourth Institute of The Second Artillery Equipment AcademeBeijingChina

Personalised recommendations