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Polychronous automata and their use for formal validation of AADL models

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Abstract

This paper investigates how state diagrams can be best represented in the polychronous model of computation (MoC) and proposes to use this model for code validation of behavior specifications in Architecture Analysis & Design Language (AADL). In this relational MoC, the basic objects are signals, which are related through dataflow equations. Signals are associated with logical clocks, which provide the capability to describe systems in which components obey multiple clock rates. We propose a model of finite-state automata, called polychronous automata, which is based on clock relationships. A specificity of this model is that an automaton is submitted to clock constraints, which allows one to specify a wide range of control-related configurations, being either reactive or restrictive with respect to their control environment. A semantic model is defined for these polychronous automata, which relies on boolean algebra of clocks. Based on a previously defined modeling method for AADL software architectures using the polychronous MoC, the proposed model is used as a formal model for the AADL behavior annex. This is illustrated with a case study involving an adaptive cruise control system.

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Acknowledgements

Jean-Pierre Talpin has been partially supported by Nankai University and by the National Natural Science Foundation of China (Grant No. 61672074).

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Authors and Affiliations

  1. Rennes-Bretagne-Atlantique Research Centre, Univ. Rennes, Inria, F-35000, Rennes, France

    Thierry Gautier, Clément Guy, Alexandre Honorat, Paul Le Guernic & Jean-Pierre Talpin

  2. Univ. Rennes, CNRS, IRISA, F-35000, Rennes, France

    Loïc Besnard

Authors
  1. Thierry Gautier
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  2. Clément Guy
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  3. Alexandre Honorat
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  4. Paul Le Guernic
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  5. Jean-Pierre Talpin
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  6. Loïc Besnard
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Corresponding author

Correspondence to Thierry Gautier.

Additional information

Thierry Gautier is researcher in Inria. He received his graduate degree from INSA Rennes (France) and PhD degree in Computer Science from the University of Rennes 1, France. He is one of the designers of the Signal language, the polychronous model of computation, and the Polychrony toolset. His main research interests focus on the safe design of complex embedded systems, including formal modeling, formal validation, transformations of models to target architectures, and synthesis of schedulers.

Clément Guy is a digital, educational, and science popularizer and facilitator. He obtained PhD degree in Software Engineering at the University of Rennes 1, France. He then worked as a research engineer in different teams at INSA of Rennes and Inria. His work focused mainly on developing new methods and tools for better, safer, and more efficient embedded software and hardware. He then completed a Master degree in techno-educational engineering. He works as a digital facilitator at the Mission locale du bassin d’emploi de Rennes, where he helps to deploy new communication tools and methods which better fit the needs of the employees. This includes audit and survey of user needs, meeting facilitating, tool deployment, and training.

Alexandre Honorat began work with the TEA team at Inria Rennes to maintain the ADFG scheduling synthesizer, after obtaining his Master’x s diploma in High Performance Computing from the ENSEIRB-MATMECA French engineering school in 2015. He also participated in linking the ADFG tool with the AADL analyzer in Polychrony, which generates Signal programs. Currently working as an engineer, he plans to study scheduling of real-time systems as a PhD student.

Paul Le Guernic graduated from Institut National des Sciences Appliquées de Rennes 1974 in France. He performed his Thèse de troisième cycle in Computer Science in 1976. From 1978 to 1984 he held a research position at Inria and served as the Directeur de Recherche in this institute since 1985. He has been head of the “Programming Environment for Real Time Applications” group, which has defined and developed the Signal language. He is one of the architects of the Polychrony toolset. Before he retired, his main research interests included the development of theories, tools, and methods for the design of realtime embedded heterogeneous systems.

Jean-Pierre Talpin is senior scientist with Inria and scientific leader of the Inria project-team TEA. Graduated in Applied Mathematics, he received a Master’s degree in Theoretical Computer Science from University Paris 6 and comleted his Ph.D. thesis at Ecole des Mines de Paris, France. He then worked three years as research associate at the European Computer-Industry Research Centre in Munich. He joined Inria in 1995 and led project-team ESPRESSO from 2000 to 2012. He is an associate editor with the ACM’s Transactions on Embedded Computer Systems. He edited three books, guest-edited a dozen scientific journal special issues with ACM and IEEE, and has authored more than one hundred journal articles, book chapters, and conference papers. He received the 2004 ACM Award for the most influential POPL paper and the 2012 ACM/IEEE LICS Test of Time Award.

Loïc Besnard is currently a senior engineer at CNRS, France. He received his PhD degree in Computer Science from University of Rennes 1, France (1992). His research interests include software reliability for the design of embedded systems: modeling, temporal analysis, formal verification, simulation, and synthesis of embedded systems. He participates in the development of the Polychony toolset based on the synchronous language Signal, the POP platform, and with the import of formalisms to AADL. He is also involved in the development of Heptane, a static worst-case execution time estimation tool.

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Gautier, T., Guy, C., Honorat, A. et al. Polychronous automata and their use for formal validation of AADL models. Front. Comput. Sci. 13, 677–697 (2019). https://doi.org/10.1007/s11704-017-6134-5

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