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Journal of Failure Analysis and Prevention

, Volume 18, Issue 6, pp 1490–1502 | Cite as

Apply DFT Integrated Enhanced EBAC Methodology on Defect Isolations

  • Wei-Ting Kary Chien
  • Yuanzi Lester YinEmail author
Technical Article---Peer-Reviewed
  • 44 Downloads

Abstract

Design for test (DFT) has been widely applied to digital circuit failure analysis (FA) in semiconductor industries. The FA methods based on DFT involve layer-by-layer checks using a polisher and an SEM for defect identification and localization. Yet these methods have limitations with high risks of sample damages. Besides, they are highly dependent on the technical proficiencies of operators and, thus, they are not effective for precise defect isolations. This problem has been aggravated, especially at advanced nodes. The nano-probing electron beam absorbed current (EBAC) has significant advantages on precisely locating defects. This technique is to directly identify specific defects without layer-by-layer checks. Therefore, it can minimize sample damages during sample pretreatment. EBAC is an efficient technique to isolate the defects when the circuit is at the floating condition. Because the ground lines exist almost everywhere in a chip and they are for, e.g., electronic static discharge charge releases or connecting with sources for pickup, EBAC becomes a natural option for us. However, due to poor EBAC images, EBAC’s applications are restricted when the circuits under test have grounding paths. In this paper, we propose two enhanced EBAC analysis methods, based on the DFT and EBAC integrated system, for the defect isolations with grounded connections. It is the first time the DFT and EBAC integrated system is reported, and we successfully demonstrated EBAC applicability by real FA cases.

Keywords

Design for test (DFT) Failure analysis (FA) Electron beam absorbed current (EBAC) Fault isolation Grounding line 

List of symbols

Iemmi

Emission current

IDDA

Analog device current

IDDD

Digital device current

Vacc

Acceleration voltage

VDD

Device working voltage

Notes

Acknowledgment

The authors would like to express thanks for the help from the colleagues of SMIC FA Lab on sample preparations and tool usages. The authors also acknowledge the financial support from “Pujiang Talent Plan” (Project No. 16PJ1433900) of Shanghai Science and Technology Committee.

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Copyright information

© ASM International 2018

Authors and Affiliations

  1. 1.Semiconductor Manufacturing International Corporation, Corp Q&RShanghaiChina

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