Modeling and Evaluation of Stacking Fault Expansion Velocity in Body Diodes of 3.3 kV SiC MOSFET
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We evaluated the stacking fault (SF) expansion velocity by electrical characteristics and estimated the screening test condition, which is a stress test with current to eliminate 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) whose forward voltage would be degraded during bipolar operation. First, double-diffused MOSFETs were fabricated, and forward current stress tests were applied to the body diodes in SiC MOSFETs. Their electrical characteristics were measured before and after forward voltage degradation at several junction temperatures. Second, to clarify the SF expansion sequence from a basal plane dislocation in the SiC epitaxial layer, continuous irradiation by an Hg lamp and photoluminescence (PL) observation were executed. Then, we present a model to explain the characteristics of the forward voltage degradation by a combination of the results of electrical measurement and PL observation. The characteristics calculated by using the presented model were in good agreement with the measured ones. Finally, forward current stress tests were applied to the body diodes in SiC MOSFETs with various conditions, and the SF expansion velocity was evaluated by calculation. These results indicate that the SF expansion velocity increases with forward current density and junction temperature. The estimated activation energy for the SF expansion velocity in the <1–100> direction is estimated to be 0.24 eV at a forward current density of 120 A/cm2.
KeywordsSiC MOSFET basal plane dislocation (BPD) stacking fault (SF) forward voltage degradation
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