Journal of Electronic Materials

, Volume 37, Issue 5, pp 646–654 | Cite as

Some Critical Materials and Processing Issues in SiC Power Devices

Open Access

There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO2 interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.


SiC SiC power devices SiC/SiO2 interface interface traps bulk traps recombination-induced stacking faults effective inversion layer electron mobility 



The authors would like to acknowledge funding support from Dr. James Scofield of the Air Force Research Laboratory, Dayton, Ohio and Mr. Charles Scozzie of the Army Research Laboratory, Adelphi, Maryland for the work on bulk traps in SiC MOS structures. The authors are indebted to Dr. H. Dietrich of the Office of Naval Research and Dr. S. Beerman-Curtin of DARPA for providing funds for the development of the 10 kV SiC MOSFETs.


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Copyright information

© TMS 2007

Authors and Affiliations

  1. 1.Cree Inc.DurhamUSA

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