Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector

  • Siew-Kei Lam
  • Teck Chuan Lim
  • Meiqing Wu
  • Bin Cao
  • Bhavan A. Jasani
Original Research Paper


Corner detection plays an essential role in many computer vision applications, e.g., object recognition, motion analysis and stereo matching. Several hardware implementations of corner detection algorithms have been previously reported to meet the real-time requirements of such applications. However, most of the reported implementations adopt similar computational flow which limit their potential for further area-time optimizations. In this paper, we propose a novel hardware design for the FAST corner detector, which unrolls the data-path to perform partial evaluation of multiple corners in a pipelined manner. We then apply logic folding that maximizes the design regularity of the unrolled data-path for resource sharing of the combinational operations. We show that the proposed design on FPGA leads to 20% reduction in critical path delay and about 39% reduction in area-delay product compared to a previously reported architecture. The real-time capability of the proposed FAST corner detectors is demonstrated on the TERASIC DE2i-150 FPGA development kit.


Corner detector FPGA Area-time optimization Data-path transposition Resource sharing 


  1. 1.
    Ehsan, S., McDonald-Maier, K.D.: On-board vision processing for small UAVs: time to rethink strategy. In: Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, pp. 75–81 (2009)Google Scholar
  2. 2.
    Schmidt, A., Kraft, M., Kasinski, A.: An evaluation of image feature detectors and descriptors for robot navigation. In: International Conference on Computer Vision and Graphics, pp. 251–259 (2010)Google Scholar
  3. 3.
    Bhaskaranand, M., Gibson, J.D.: Low-complexity video encoding for UAV reconnaissance and surveillance. Mil. Commun. Conf. 6375, 251–259 (2011)Google Scholar
  4. 4.
    Gauglitz, S., Hollerer, T., Turki, M.: Evaluation of interest point detectors and feature descriptors for visual tracking. Int. J., Comput. Vis. 94, 335–360 (2011)CrossRefzbMATHGoogle Scholar
  5. 5.
    Gil, A., Mozos, O., Ballesta, M., Reinoso, O.: A comparative evaluation of interest point detectors and local descriptors for visual SLAM. Mach. Vis. Appl. 21, 905–920 (2010)CrossRefGoogle Scholar
  6. 6.
    Ramakrishnan, N., Wu, M., Lam, S.-K., Srikanthan, T.: Enhanced low complexity pruning for corner detection. J. Real Time Image Process. 12(1), 197–213 (2011)CrossRefGoogle Scholar
  7. 7.
    Harris, C., Stephens, M.: A combined corner and edge detector. In: Proceedings of the Fourth Alvey Vision Conference, pp. 147–151 (1988)Google Scholar
  8. 8.
    Kraft, M., Schmidt, A., Kasinski, A.J.: High-speed image feature detection using FPGA implementation of FAST algorithm. In: Proceedings of the Third International Conference on Computer Vision Theory and Applications (VISAPP 2008), Funchal, Portugal, 22–25 January 2008, pp. 174–179 (2008)Google Scholar
  9. 9.
    Dohi, K., Yorita, Y., Shibata, Y., Oguri, K.: Pattern compression of fast corner detection for efficient hardware implementation. In: International Conference on Field Programmable Logic and Applications, pp. 478–481 (2011)Google Scholar
  10. 10.
    Amaricai, A., Gavriliu, C.E., Boncalo, O.: An FPGA sliding window-based architecture Harris corner detector. In: International Conference on Field Programmable Logic and Applications (2014)Google Scholar
  11. 11.
    Soberl, D., Zimic, N., Leonardis, A., Krivic, J., Moskon, Miha: Hardware implementation of FAST algorithm for mobile applications. J. Signal Process. Syst. 79(3), 247–256 (2015)CrossRefGoogle Scholar
  12. 12.
    Fularz, M., Kraft, M., Schmidt, A., Kasinski, A.: A high-performance FPGA-based image feature detector and matcher based on the FAST and BRIEF algorithms. Int. J. Adv. Robot. Syst. 12, 141 (2015). doi: 10.5772/61434 CrossRefGoogle Scholar
  13. 13.
    Orabi, H., Shaikh-Husin, N., Ullah Sheikh, U.: Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications. In: International Conference on Digital Information Management, pp. 164–168 (2015)Google Scholar
  14. 14.
    Hernandez-Lopez, A., Torres-Huitzil, C., Garcia-Hernandez, J.J.: FPGA-based flexible hardware architecture for image interest point detection. Int. J. Adv. Robot. Syst. 12, 93 (2015). doi: 10.5772/61058 CrossRefGoogle Scholar
  15. 15.
    Chao, T.L., Wong, K.H.: An efficient FPGA implementation of the Harris corner feature detector. In: 2015 14th IAPR International Conference on Machine Vision Applications (MVA), pp. 89–93. IEEE (2015)Google Scholar
  16. 16.
    Rosten, E., Drummond, T.: Fusing points and lines for high performance tracking. In: International Conference on Computer Vision, pp. 1508–1515 (2005)Google Scholar
  17. 17.
    Rosten, E., Drummond, T.: Machine learning for high speed corner detection. In: European Conference on Computer Vision, pp. 430–443 (2006)Google Scholar
  18. 18.
    Rosten, E., Porter, R., Drummond, T.: Faster and better: a machine learning approach to corner detection. IEEE Trans. Pattern Anal. Mach. Intell. 32, 105–119 (2010)CrossRefGoogle Scholar
  19. 19.
    Mehra, R., Rabaey, J.: Exploiting regularity for low-power design. In: IEEE/ACM International Conference on Computer-Aided Design, pp. 166–172 (1996)Google Scholar
  20. 20.
    Canis, A., Anderson, J.H., Brown, S.D.: Multi-pumping for resource reduction in FPGA high-level synthesis. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 194–197 (2013)Google Scholar
  21. 21.
    Tuytelaars, T., Mikolajczyk, K.: Local invariant feature detectors: a survey. Found. Trends Comput. Graph. Vis. 3(3), 177–280 (2008)CrossRefGoogle Scholar
  22. 22.
    Schmid, C., Mohr, R., Bauckhage, C.: Evaluation of interest point detectors. Int. J. Comput. Vis. 37(2), 151–172 (2000)CrossRefzbMATHGoogle Scholar
  23. 23.
    Jianbo, S., Tomasi, C.: Good features to track. In: Computer Vision and Pattern Recognition, pp. 593–600 (1994)Google Scholar
  24. 24.
    Smith, S.M., Brady, J.M.: SUSAN—a new approach to low level image processing. Int. J. Comput. Vis. 23, 45–78 (1997)CrossRefGoogle Scholar
  25. 25.
    Chih-Chi, C., Chia-Hua, L., Chung-Te, L., Chang, S.C., Liang-Gee, C.: iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor. In: Design Automation Conference, p. 9095 (2008)Google Scholar
  26. 26.
    Saidani, T., Lacassagne, L., Bouaziz, S., Khan, T.: Parallelization strategies for the points of interests algorithm on the cell processor. Parallel Distrib. Process. Appl. 4742, 104–112 (2007)CrossRefGoogle Scholar
  27. 27.
    Hosseini, F., Fijany, A., Fontaine, J.-G.: Highly parallel implementation of Harris Corner detector on CSX SIMD architecture. In: Guarracino, M.R., et al. (eds.) Euro-Par 2010 Parallel Processing Workshops. Euro-Par 2010. Lecture Notes in Computer Science, vol. 6586, pp. 137–144. Springer, Berlin, Heidelberg (2011)Google Scholar
  28. 28.
    Piskorski, S., Lacassagne, L., Bouaziz, S., Etiemble, D.: Customizing CPU instructions for embedded vision systems. In: Proceedings of the 2007 IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 59–64 (2007)Google Scholar
  29. 29.
    Tippetts, B., Lee, D.-J., Archibald, J.: An on-board vision sensor system for small unmanned vehicle applications. Mach. Vis. Appl. 23(2), 113 (2012)Google Scholar
  30. 30.
    Benedetti, A., Perona, P.: Real-time 2-D feature detection on a reconfigurable computer. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. 586–593 (1998)Google Scholar
  31. 31.
    Claus, C., Huitl, R., Rausch, J., Stechele, W.: Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. In: Field Programmable Logic and Applications, pp. 138–145 (2009)Google Scholar
  32. 32.
    Rublee, E., Rabaud, V., Konolige, K., Bradski, G.: ORB: an efficient alternative to SIFT or SURF. In: ICCV 2011, pp. 2564–2571 (2011)Google Scholar
  33. 33.
    Leutenegger, S., Chli, M., Siegwart, R.Y.: BRISK: binary robust invariant scalable keypoints. In: IEEE International Conference on Computer Vision, pp. 2548–2555 (2011)Google Scholar
  34. 34.
    Mur-Artal, R., Montiel, J.M.M., Tardos, J.D.: ORB-SLAM: a versatile and accurate monocular SLAM system. IEEE Trans. Robot. 31(5), 1147–1163 (2015)CrossRefGoogle Scholar
  35. 35.
    Canziani, A., Paszke, A., Culurciello, E.: An Analysis of Deep Neural Network Models for Practical Applications. arXiv:1605.07678 (2017)
  36. 36.

Copyright information

© Springer-Verlag GmbH Germany 2017

Authors and Affiliations

  1. 1.School of Computer Science and EngineeringNanyang Technological UniversitySingaporeSingapore

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