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Journal of Real-Time Image Processing

, Volume 13, Issue 1, pp 71–83 | Cite as

Real-time scalable hardware architecture for 3D-HEVC bipartition modes

  • Gustavo SanchezEmail author
  • César Marcon
  • Luciano Agostini
Special Issue Paper

Abstract

This article presents a real-time scalable hardware architecture for the bipartition modes of 3D high-efficiency video coding (3D-HEVC) standard, which includes the depth modeling modes 1 (DMM-1) and 4 (DMM-4). A simplification of the DMM-1 algorithm was done, removing the refinement step. This simplification causes a small BD-rate increase (0.09 %) with the advantage of better using our hardware resources, reducing the necessary memory required for storing all DMM-1 wedgelet patterns by 30 %. The scalable architecture can be configured to support all the different block sizes supported by the 3D-HEVC and also to reach different throughputs, according to the application requirements. Then, the proposed solution can be efficiently used for several encoding scenarios and many different applications. Synthesis results considering a test case show that the designed architecture is capable of processing HD 1080p videos in real time, but with other configurations, higher resolutions are also possible to be processed.

Keywords

3D-HEVC Bipartition modes Scalable architecture Hardware design 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Gustavo Sanchez
    • 1
    Email author
  • César Marcon
    • 1
  • Luciano Agostini
    • 2
  1. 1.PPGCC – PUCRSPorto AlegreBrazil
  2. 2.GACI - PPGC – UFPELPelotasBrazil

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