Advertisement

Journal of Real-Time Image Processing

, Volume 16, Issue 2, pp 547–557 | Cite as

Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder

  • Estefania AlcocerEmail author
  • Roberto Gutierrez
  • Otoniel Lopez-Granado
  • Manuel P. Malumbres
Original Research Paper

Abstract

High-Efficiency Video Coding (HEVC) was developed to improve its predecessor standard, H264/AVC, by doubling its compression efficiency. As in previous standards, Motion Estimation (ME) is one of the encoder critical blocks to achieve significant compression gains. However, it demands an overwhelming complexity cost to accurately remove video temporal redundancy, especially when encoding very high-resolution video sequences. To reduce the overall video encoding time, we propose the implementation of the HEVC ME block in hardware. The proposed architecture is based on (a) a new memory scan order, and (b) a new adder tree structure, which supports asymmetric partitioning modes in a fast and efficient way. The proposed system has been designed in VHDL (VHSIC Hardware Description Language), synthesized and implemented by means of the Xilinx FPGA, Virtex-7 XC7VX550T-3FFG1158. Our design achieves encoding frame rates up to 116 and 30 fps at 2 and 4K video formats, respectively.

Keywords

HEVC FPGA Integer motion estimation Inter-prediction SAD architecture 

Notes

Acknowledgments

This research was supported by the Spanish Ministry of Economy and Competitiveness under Grant TIN2015-66972-C5-4-R.

References

  1. 1.
    Sullivan, G.J., Ohm, J.R., Han, W.J., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22, 1649–1668 (2012)CrossRefGoogle Scholar
  2. 2.
    Sze, V., Budagavi, M., Sullivan, G.J.: High Efficiency Video Coding (HEVC) Algorithms and Architectures. Springer, Switzerland (2014)Google Scholar
  3. 3.
    Medhat, A., Shalaby, A., Sayed, M.S., Elsabrouty, M.: A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder. In: IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), pp. 280–283. Ishigaki (2014)Google Scholar
  4. 4.
    Byun, J., Jung, Y., Kim, J.: Design of integer motion estimator of HEVC for asymmetric motion-partitioning mode and 4K-UHD. Electron. Lett. 49(18), 1142–1143 (2013)CrossRefGoogle Scholar
  5. 5.
    Vidyalekshmi V.G., Yagain D., Ganesh Rao K.: Motion estimation block for HEVC encoder on FPGA. In: IEEE Int. Conf. Recent Advances and Innovations in Engineering (ICRAIE), pp. 1–5. Jaipur, (2014)Google Scholar
  6. 6.
    Yuan, X., Jinsong, L., Liwei, G., Zhi, Z., Teng, R.K.F.: A high performance VLSI architecture for integer motion estimation in HEVC. In: IEEE 10th Int. Conf. ASIC (ASICON), pp. 1–4. Shenzhen (2013)Google Scholar
  7. 7.
    D’huys, T.: Reconfigurable data flow engine for HEVC motion estimation. In: IEEE Int. Conf. Image Processing (ICIP), pp. 1223–1227. Paris (2014)Google Scholar
  8. 8.
    Davis, P., Sangeetha, M.: Implementation of motion estimation algorithm for H.265/HEVC. Int. J. Adv. Res. Elect. Electron. Instrum. Eng. 3(3), 122–126 (2014)Google Scholar
  9. 9.
    Nalluri, P., Alves, L.N., Navarro, A.: High speed SAD architectures for variable block size motion estimation in HEVC video coding. In: IEEE Int. Conf. Image Processing (ICIP), pp. 1233–1237. Paris (2014)Google Scholar
  10. 10.
    Chen, C.Y., Chien, S.Y., Huang, Y.W., Chen, T.C., Wang, T.C., Chen, L.G.: Analysis and architecture design of variable block-size motion estimation for H.264/AVC. IEEE Trans. Circuits Syst I: Reg. Papers 53(3), 578–893 (2006)CrossRefGoogle Scholar
  11. 11.
    Elhamzi, W., Dubois, J., Miteran, J.: An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding. Springer J. Real-Time Process. 9(1), 19–30 (2014)CrossRefGoogle Scholar
  12. 12.
    Moorthy, T., Ye, A.: A scalable architecture for variable block size motion estimation on field-programmable gate arrays. In: IEEE Canadian Conf. Electrical and Computer Engineering (CCECE), pp. 1303–1308. Niagara Falls (2008)Google Scholar
  13. 13.
    Kthiri, M., Kadionik, P., Levi, H., Loukil, H., Atitallah,,B., Masmoudi, N.: An FPGA implementation of motion estimation algorithm for H.264/AVC. In: IEEE 5th Int. Symp. I/V Communications and Mobile Network (ISVC), pp. 1–4. Rabat (2010)Google Scholar
  14. 14.
    Pastuszak, G., Jakubowski, M.: Adaptive computationally scalable motion estimation for the hardware H.264/AVC encoder. IEEE Trans. Circuits Syst. Video Technol. 23(5), 802–812 (2013)CrossRefGoogle Scholar
  15. 15.
    Pastuszak, G., Trochimiuk, M.: Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder. J. Real Time Image Process (2015)Google Scholar
  16. 16.
    Lin, Y.L.S., Kao, C.Y., Kuo, H.C., Hen, J.W.: VLSI Design for Video Coding-H.264/AVC Encoding from Standard Specification to Chip. Springer, New York (2010)CrossRefzbMATHGoogle Scholar
  17. 17.
    HEVC software repository HM–14.0 reference model. https://hevc.hhi.fraunhofer.de/trac/hevc/browser/tags/HM-14.0. Accessed 2 May 2014 (2014)

Copyright information

© Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Estefania Alcocer
    • 1
    Email author
  • Roberto Gutierrez
    • 2
  • Otoniel Lopez-Granado
    • 1
  • Manuel P. Malumbres
    • 1
  1. 1.Physics and Computer Architecture departmentMiguel Hernandez University of ElcheAlicanteSpain
  2. 2.Communication Engineering departmentMiguel Hernandez University of ElcheAlicanteSpain

Personalised recommendations