Journal of Real-Time Image Processing

, Volume 15, Issue 4, pp 787–797 | Cite as

An FPGA implementation for real-time edge detection

  • Jie JiangEmail author
  • Chang Liu
  • Sirui Ling
Original Research Paper


The Hessian matrix-based edge detection algorithm of Dr. Carsten Steger has the advantages of high accuracy and versatility. However, this algorithm has a complex and time-consuming computation process. Large-scale Gaussian convolution also employs a large number of multipliers when implemented on a field programmable gate array (FPGA). To address these problems, an FPGA implementation for Steger’s edge detection algorithm is proposed. This implementation employs pipeline and parallel architectures at both task and data levels for data stream processing. The original kernels of Gaussian convolution are simplified with box-filter to convert the multiplication operation in the convolution into addition, subtraction, or shift operations with the concept of integral image, thereby minimizing the multiplier resources. The proposed FPGA implementation demonstrates a favorable accuracy and anti-noise capability when dealing with different degrees of blur and noise in an image. Therefore, the FPGA implementation can satisfy real-time edge detection requirements.


Real-time image processing Edge detection Differential convolution FPGA 



This research is supported by the National Natural Science Fund of China under Grant [No. 61222304] and by the Specialized Research Fund for the Doctoral Program of Higher Education of China under Grant [No. 20121102110032]. The authors are grateful for all the valuable suggestions that they have received during the course of this work.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2015

Authors and Affiliations

  1. 1.Key Laboratory of Precision Opto-Mechatronics TechnologyMinistry of Education, Beihang UniversityBeijingChina

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