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Journal of Real-Time Image Processing

, Volume 13, Issue 2, pp 397–414 | Cite as

Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling

Original Research Paper

Abstract

Video processing algorithms are computationally intensive and place stringent requirements on performance and efficiency of memory bandwidth and capacity. As such, efficient hardware accelerations are inevitable for fast video processing systems. In this paper, we propose resource- and power-optimized FPGA-based configurable architecture for video object detection by integrating noise estimation, Mixture-of-Gaussian background modeling, motion detection, and thresholding. Due to large amount of background modeling parameters, we propose a novel Gaussian parameter compression technique suitable for resource- and power-constraint embedded video systems. The proposed architecture is simulated, synthesized and verified for its functionality, accuracy and performance on a Virtex-5 FPGA-based embedded platform by directly interfacing to a digital video input. Intentional exploitation of heterogeneous resources in FPGAs, and advanced design techniques such as heavy pipelining and data parallelism yield real-time processing of HD-1080p video streams at 30 frames per second. Objective and subjective evaluations to existing hardware-based methods show that the proposed architecture obtains orders of magnitude performance improvements, while utilizing minimal hardware resources. This work is an early attempt to devise a complete video surveillance system onto a stand-alone resource-constraint FPGA-based smart camera.

Keywords

Field-programmable gate arrays FPGA Video signal processing Noise Moving objects Motion detection Thresholding Gaussian background update Gaussian parameter compression 

Notes

Acknowledgments

This work was supported, in part, by the Fonds de la recherche sur la nature et les technologies du Quebec (NATEQ).

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Copyright information

© Springer-Verlag Berlin Heidelberg 2014

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringConcordia UniversityMontréalCanada

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