Journal of Real-Time Image Processing

, Volume 9, Issue 1, pp 141–157 | Cite as

High performance implementation of texture features extraction algorithms using FPGA architecture

  • Ali Reza Akoushideh
  • Asadollah Shahbahrami
  • Babak Mazloom-Nezhad Maybodi
Special Issue

Abstract

The most popular second-order statistical texture features are derived from the co-occurrence matrix, which has been proposed by Haralick. However, the computation of both matrix and extracting texture features are very time consuming. In order to improve the performance of co-occurrence matrices and texture feature extraction algorithms, we propose an architecture on FPGA platform. In the proposed architecture, first, the co-occurrence matrix is computed then all thirteen texture features are calculated in parallel using computed co-occurrence matrix. We have implemented the proposed architecture on Virtex 5 fx130T-3 FPGA device. Our experimental results show that a speedup of 421[× yields over a software implementation on Intel Core i7 2.0 GHz processor. In order to improve much more performance on textures, we have reduced the computation of 13 texture features to 3 texture features using ranking of Haralick’s features. The performance improvement is 484×.

Keywords

Haralick texture feature Image processing FPGA 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Ali Reza Akoushideh
    • 1
  • Asadollah Shahbahrami
    • 2
  • Babak Mazloom-Nezhad Maybodi
    • 1
  1. 1.Electrical and Computer DepartmentShahid-Beheshti University, G.CTehranIran
  2. 2.Department of Computer EngineeringUniversity of GuilanRashtIran

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