Journal of Real-Time Image Processing

, Volume 2, Issue 4, pp 179–190 | Cite as

Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems

  • Heather Quinn
  • Miriam Leeser
  • Laurie Smith King
Special Issue


The Dynamo system provides a runtime environment for mapping image processing applications to hardware/software platforms that contain a mix of processors and reconfigurable hardware. Dynamo can be used by an image analyst with no knowledge of HW/SW design. The analyst specifies the algorithms implemented in a processing pipeline and the input data. Dynamo dynamically selects the most efficient combination of hardware and software component implementations to minimize pipeline runtime, generates the source code that implements the pipeline, processes the input data using the implementation, and returns the results. We present the design and implementation of Dynamo. Our target domain is image processing pipelines. We chose image processing (IP) because many IP algorithms benefit from acceleration using reconfigurable hardware and many IP applications are structured as a pipeline, where each component can be implemented in software or hardware. Our performance modeling incorporates profiles based on experimental results and on overhead costs. Our results show that modeling of overhead costs is essential to choosing the correct implementation. We illustrate how Dynamo chooses a mix of hardware and software implementations to minimize runtime for several different image processing applications.


Communication Cost Software Implementation Overhead Cost Absolute Relative Error Interface Type 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



Heather Quinn was supported under a Graduate Student Researchers Program Fellowship through NASA’s Goddard Space Flight Center when this research was conducted. This work was supported in part by CenSSIS, the Center for Subsurface Sensing and Imaging Systems, under the Engineering Research Centers Program of the National Science Foundation (award number EEC-9986821). This research was also supported in part by NSF award number EHS-0410246. Heather Quinn is currently employed at Los Alamos National Laboratory. This paper was cleared for public release as LA-UR-06-3434; distribution is unlimited. Los Alamos National Laboratory, an affirmative action/equal opportunity employer, is operated by the University of California for the U.S. Department of Energy under contract W-7405-ENG-36. By acceptance of this article, the publisher recognizes that US Government retains a nonexclusive, royalty-free license to publish or reproduce the published form of this contribution, or to allow others to do so, for US Government purposes. Los Alamos National Laboratory requests that the publisher identify this article as work performed under the auspices of the US Department of Energy. Los Alamos National Laboratory strongly supports academic freedom and a researcher’s right to publish; as an institution, however, the Laboratory does not endorse the viewpoint of a publication or guarantee its technical correctness.


  1. 1.
    ACCP.: Altera Accelchip., last visited May 2007 (2006)
  2. 2.
    Annapolis Microsystems.: Annapolis wildcard., last visited May 2007 (2006)
  3. 3.
    Banerjee, S., Bozorgzadeh, E., Dutt, N.: Physically-aware HW–SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. In: Design Automation Conference (DAC), pp. 335–340 (2005)Google Scholar
  4. 4.
    Bobda, C., Ahmadinia, A.: Dynamic interconnection of reconfigurable modules on reconfigurable devices. Des. Test Comput. 22, 443– 451 (2005)CrossRefGoogle Scholar
  5. 5.
    CEL.: Celoxica., last visited May 2007 (2007)
  6. 6.
    DBLD.: Altera DSP Builder., last visited May 2007 (2007)
  7. 7.
    Eclipse.: Eclipse., last visited May 2007 (2006)
  8. 8.
    Eclipsecolorer.: Eclipsecolorer profiling tool. projects/eclipsecolorer/, last visited May 2007 (2006)
  9. 9.
    Fu, W., Compton, K.: An execution environment for reconfigurable computing. In: Field-programmable Custom Computing Machines (FCCM), pp. 149–158 (2005)Google Scholar
  10. 10.
    Gupta, R.K., Jr CJNC, Micheli, G.D.: Synthesis and simulation of digital systems containing interacting hardware and software components. In: Design Automation Conference (DAC), pp. 225–230 (1992)Google Scholar
  11. 11.
    Kalavade, A., Lee, E.: A gobal criticality/local phase driven algorithm for the constrainted hardware/software partitioning problem. In: Third International Workshop on Hardware/Software Co-design (Codes/CASHE ’94), pp. 42–48 (1994)Google Scholar
  12. 12.
    King, L.A.S, Quinn, H., Leeser, M., et al.: Run-time execution of reconfigurable hardware in a Java environment. In: International Conference on Computer Design (ICCD), pp. 380–387 (2001)Google Scholar
  13. 13.
    King, L.A.S., Leeser, M., Quinn, H.: Dynamo: A runtime partitioning system. In: International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 145–154 (2004)Google Scholar
  14. 14.
    Levine, B.A., Schmit, H.: Efficient application representation for HASTE: hybrid architectures with a single, transformable executable. In: Field Programmable Custom Computing Machines (FCCM), pp. 101–110 (2003)Google Scholar
  15. 15.
    Maestre, R., Kurdahi, F.J., Fernandez, M., Hermida, R., Bagherzadeh, N., Singh, H.: A framework for reconfigurable computing: task scheduling and context management. IEEE Transactions on very Large Scale Integration (VLSI) Systems 9(6), 858–873 (2001). doi: 10.1109/92.974899 CrossRefGoogle Scholar
  16. 16.
    Mittal, G., Zaretsky, D., Tang, X., Banerjee, P.: Automatic translation of software binaries onto FPGAs. In: 41st Design Automation Conference (DAC), pp. 389–394 (2004)Google Scholar
  17. 17.
    Niemann, R., Marwedel, P.: Hardware/software partitioning using Integer Programming. In: European Design and Test Conference, pp. 473–480 (1996)Google Scholar
  18. 18.
    Noguera, J., Badia, R.M.: Hw/sw codesign techniques for dynamically reconfigurable architectures. IEEE Transactions on very Large Scale Integration (VLSI) Systems 10(4), 399–415 (2002). doi: 10.1109/TVLSI.2002.801575 CrossRefGoogle Scholar
  19. 19.
    Ong, S., Kerkiz, N., Srijanto, B., Tan, C., Langston, M., Newport, D., Bouldin, D.: Automatic mapping of multiple applications to multiple adaptive computing systems. In: Field-programmable Custom Computing Machines (FCCM), pp. 218–227 (2001)Google Scholar
  20. 20.
    Passerone, R., Rowson, J.A., Sangiovanni-Vincentelli, A.L.: Automatic synthesis of interfaces between incompatible protocols. In: Design Automation Conference (DAC), pp. 8–13 (1998)Google Scholar
  21. 21.
    Quinn, H.: Runtime tools for hardware/software systems with reconfigurable hardware. PhD thesis, Department of Electrical and Computer Engineering, Northeastern University, available from (2004)
  22. 22.
    Quinn, H., King, L.A.S, Leeser, M., Meleis, W.: Runtime assignment of reconfigurable hardware components for image processing pipelines. In: Field Programmable Custom Computing Machines (FCCM), pp. 173–184 (2003)Google Scholar
  23. 23.
    SGEN.: Xilinx System Generator., last visited May 2007 (2007)
  24. 24.
    Siozios, K., Koutroumpezis, G., Tatas, K., Soudris, D., Thanailakis, A.: Dagger: A novel generic methodology for fpga bitstream generation and its software tool implementation. In: 19th International Parallel and Distributed Processing Symposium (IPDPS) (2005)Google Scholar
  25. 25.
    Srivastava, M.B., Yanbing, L., Callahan, T., Darnell, E., Harr, R., Kurkure, U., Stockwood, J.: Hardware–software co-design of embedded reconfigurable architectures. In: Design Automation Conference, IEEE (2000)Google Scholar
  26. 26.
    Stitt, G., Lysecky, R., Vahid, F.: Dynamic hardware/software partitioning: A first approach. In: Design Automation Conference, pp. 250–255 (2003)Google Scholar
  27. 27.
    Stitt, G., Vahid, F., McGregor, G., Einloth, B.: Hardware/software partitioning of software binaries: a case study of H.264 decode. In: 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), pp. 285–290 (2005)Google Scholar
  28. 28.
    STRTCH.: Stretch s5000 Software-configurable Processors., last visited May 2007 (2007)
  29. 29.
    V2PRO.:Xilinx Virtex-II Pro., last visited May 2007 (2007)
  30. 30.
    Wiangtong, T., Cheung, P., Luk, W.: Tabu search with intensification strategy for functional partitioning in hardware–software codesign. In: Field-programmable Custom Computing Machines (FCCM), pp. 297–298 (2002)Google Scholar
  31. 31.
    XTREM.: Xtremedata., last visited May 2007 (2007)

Copyright information

© Springer-Verlag 2007

Authors and Affiliations

  • Heather Quinn
    • 1
  • Miriam Leeser
    • 2
  • Laurie Smith King
    • 3
  1. 1.Los Alamos National LaboratoryLos AlamosUSA
  2. 2.Northeastern UniversityBostonUSA
  3. 3.College of the Holy CrossWorcesterUSA

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