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Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing

  • Runze Han
  • Peng Huang
  • Yudi Zhao
  • Xiaole Cui
  • Xiaoyan Liu
  • Jinfeng Kang
Research Paper
  • 22 Downloads

Abstract

Crossbar architecture has been considered as an efficient means to execute a matrix-vector multiplication computation. An efficient evaluation model for this computation including the interconnect resistance effect on the high density resistive random access memmory (RRAM) crossbar array is proposed in this paper. The proposed model considers the interconnect resistance impacts on the columns and rows separately. The simulation results indicate that the computing speed of the proposed model can be boosted by over three orders of magnitude with the computation deviation of 7.7% in comparison with the precise comprehensive model in the 64 kb crossbar array fabricated at the 14 nm technology node. Based on the proposed evaluation model, the impacts of the parameters including nonlinearity and load resistance, on the computation are discussed along with solutions to improve the computational performance.

Keywords

crossbar array evaluation model interconnect resistance matrix-vector multiplication RRAM 

Notes

Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant Nos. 61334007, 61421005), and Shenzhen Science and Technology Innovation Committee (Grant No. JCYJ2017041215-0411676).

References

  1. 1.
    Wong H S P, Lee H Y, Yu S, et al. Metal-oxide RRAM. Proc IEEE, 2012, 100: 1951–1970CrossRefGoogle Scholar
  2. 2.
    Hudec B, Hsu C W, Wang I T, et al. 3D resistive RAM cell design for high-density storage class memory-a review. Sci China Inf Sci, 2016, 59: 061403CrossRefGoogle Scholar
  3. 3.
    Waser R, Dittmann R, Staikov G, et al. Redox-based resistive switching memories: nanoionic mechanisms, prospects, and challenges. Adv Mater, 2009, 21: 2632–2663CrossRefGoogle Scholar
  4. 4.
    Borghetti J, Snider G S, Kuekes P J, et al. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature, 2010, 464: 873–876CrossRefGoogle Scholar
  5. 5.
    Yang J J, Strukov D B, Stewart D R. Memristive devices for computing. Nat Nanotech, 2013, 8: 13–24CrossRefGoogle Scholar
  6. 6.
    Huang P, Kang J F, Zhao Y D, et al. Reconfigurable nonvolatile logic operations in resistance switching crossbar array for large-scale circuits. Adv Mater, 2016, 28: 9758–9764CrossRefGoogle Scholar
  7. 7.
    Hu M, Li H, Chen Y R, et al. Memristor crossbar-based neuromorphic computing system: a case study. IEEE Trans Neural Netw Learn Syst, 2014, 25: 1864–1878CrossRefGoogle Scholar
  8. 8.
    Upadhyay N K, Joshi S, Yang J J. Synaptic electronics and neuromorphic computing. Sci China Inf Sci, 2016, 59: 061404CrossRefGoogle Scholar
  9. 9.
    Cao J D, Li R X. Fixed-time synchronization of delayed memristor-based recurrent neural networks. Sci China Inf Sci, 2017, 60: 032201CrossRefGoogle Scholar
  10. 10.
    Yu S M, Gao B, Fang Z, et al. A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation. Adv Mater, 2013, 25: 1774–1779CrossRefGoogle Scholar
  11. 11.
    Hu M, Li H, Wu Q, et al. Hardware realization of BSB recall function using memristor crossbar arrays. In: Proceedings of the 49th Annual Design Automation Conference, San Francisco, 2012. 498–503Google Scholar
  12. 12.
    Gu P, Li B X, Tang T Q, et al. Technological exploration of RRAM crossbar array for matrix-vector multiplication. In: Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, 2015. 106–111Google Scholar
  13. 13.
    Gao L G, Chen P Y, Yu S M. Demonstration of convolution kernel operation on resistive cross-point array. IEEE Electron Device Lett, 2016, 37: 870–873CrossRefGoogle Scholar
  14. 14.
    Li H T, Gao B, Chen Z, et al. A learnable parallel processing architecture towards unity of memory and computing. Sci Rep, 2015, 5: 013330CrossRefGoogle Scholar
  15. 15.
    Semiconductor Industry Association. International Technology Roadmap for Semiconductors. 2015. https://www. semiconductors.org/main/2015 international technology roadmap for semiconductors itrs/Google Scholar
  16. 16.
    Chen A. A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics. IEEE Trans Electron Device, 2013, 60: 1318–1326CrossRefGoogle Scholar
  17. 17.
    Vontobel P O, Robinett W, Kuekes P J, et al. Writing to and reading from a nano-scale crossbar memory based on memristors. Nanotechnology, 2009, 20: 425204CrossRefGoogle Scholar
  18. 18.
    Deng Y X, Huang P, Chen B, et al. RRAM crossbar array with cell selection device: a device and circuit interaction study. IEEE Trans Electron Device, 2013, 60: 719–726CrossRefGoogle Scholar
  19. 19.
    Huang P, Liu X Y, Chen B, et al. A physics-based compact model of metal-oxide-based RRAM DC and AC operations. IEEE Trans Electron Device, 2013, 60: 4090–4097CrossRefGoogle Scholar
  20. 20.
    Sheridan P M, Cai F X, Du C, et al. Sparse coding with memristor networks. Nat Nanotech, 2017, 12: 784–789CrossRefGoogle Scholar
  21. 21.
    Li C, Hu M, Li Y N, et al. Analogue signal and image processing with large memristor crossbars. Nat Electron, 2018, 1: 52–59CrossRefGoogle Scholar

Copyright information

© Science China Press and Springer-Verlag GmbH Germany, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Institute of MicroelectronicsPeking UniversityBeijingChina
  2. 2.Key Lab of Integrated MicrosystemsPeking University Shenzhen Graduate SchoolShenzhenChina

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