Design for manufacturability and reliability in extreme-scaling VLSI

  • Bei Yu
  • Xiaoqing Xu
  • Subhendu Roy
  • Yibo Lin
  • Jiaojiao Ou
  • David Z. Pan
Review Special Focus on Advanced Microelectronics Technology

Abstract

In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore’s law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

Keywords

design for manufacturability design for reliability VLSI CAD 

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Copyright information

© Science China Press and Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Bei Yu
    • 1
    • 2
  • Xiaoqing Xu
    • 2
  • Subhendu Roy
    • 2
    • 3
  • Yibo Lin
    • 2
  • Jiaojiao Ou
    • 2
  • David Z. Pan
    • 2
  1. 1.CSE DepartmentThe Chinese University of Hong KongNT Hong KongChina
  2. 2.ECE DepartmentUniversity of Texas at AustinAustinUSA
  3. 3.Cadence Design Systems, Inc.San JoseUSA

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