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Single event upset rate modeling for ultra-deep submicron complementary metal-oxide-semiconductor devices

  • Liang HeEmail author
  • Hua Chen
  • Peng Sun
  • Xiaofei Jia
  • Chongguang Dai
  • Jing Liu
  • Long Shao
  • Zhaoqing Liu
Research Paper

Abstract

Based on the integral method of single event upset (SEU) rate and an improved charge collection model for ultra-deep submicron complementary metal-oxide-semiconductor (CMOS) devices, three methods of SEU rate calculation are verified and compared. The results show that the integral method and the figure of merit (FOM) methods are basically consistent at the ultra-deep submicron level. By proving the validity of the carrier collection model considering charge sharing, the applicability of two FOM methods is verified, and the trends of single-bit and multiple-bit upset rates for ultra-deep submicron CMOS are analyzed.

Keywords

ultra-deep submicron complementary metal-oxide-semiconductor devices single event upset rates charge sharing 

References

  1. 1.
    McMorrow D, Khachatrian A, Roche N J-H, et al. Single-Event upsets in substrate-etched CMOS SOI SRAMs using ultraviolet optical pulses with sub-Micrometer spot size. IEEE Trans Nucl Sci, 2013; 60: 4184–4191CrossRefGoogle Scholar
  2. 2.
    He Y B, Chen S M. Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology. Sci China Inf Sci, 2014, 57: 102405Google Scholar
  3. 3.
    Wang Z M, Yao Z B, Guo H X, et al. Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs. Sci China Inf Sci, 2012; 55: 971–982CrossRefGoogle Scholar
  4. 4.
    Moukhtari I E, Pouget V, Larue C, et al. Impact of negative bias temperature instability on the single-event upset threshold of a 65 nm SRAM cell. Microelectron Rel, 2013; 53: 1325–1328CrossRefGoogle Scholar
  5. 5.
    Petersen E L, Koga R, Shoga M A, et al. The single event revolution. IEEE Trans Nucl Sci, 2013; 60: 1824–1835CrossRefGoogle Scholar
  6. 6.
    Raine M, Hubert G, Paillet P, et al. Implementing realistic heavy ion tracks in a SEE prediction tool: comparison between different approaches. IEEE Trans Nucl Sci, 2012; 59: 950–957CrossRefGoogle Scholar
  7. 7.
    Amusan O A, Witulski A F, Massengill LW, et al. Charge collection and charge sharing in a 130 nm CMOS technology. IEEE Trans Nucl Sci, 2006; 53: 3253–3258CrossRefGoogle Scholar
  8. 8.
    Amusan O A, Massengill L W, Baze M P, et al. Single event upsets in deep-submicrometer technologies due to charge sharing. IEEE Trans Dev Mater Rel, 2008; 8: 582–589CrossRefGoogle Scholar
  9. 9.
    Blum D R. Hardened by design approaches for mitigating transient faults in memory-based systems. Dissertation for the Doctoral Degree. Pullman: Washington State University, 2007Google Scholar
  10. 10.
    Tipton A D, Pellish J A, Reed R A, et al. Multiple-bit upset in 130 nm CMOS technology. IEEE Trans Nucl Sci, 2006; 53: 3259–3264CrossRefGoogle Scholar
  11. 11.
    Connel L W, McDaniel P J, Prinja A K, et al. Modeling the heavy ion upset cross section. IEEE Trans Nucl Sci, 1995; 42: 73–82CrossRefGoogle Scholar
  12. 12.
    Connell L W, Sexton F W, Prinja A K. Further development of the heavy ion cross section for single event upset: model (HICUP). IEEE Trans Nucl Sci, 1995; 42: 2026–2034CrossRefGoogle Scholar
  13. 13.
    Foro L L, Touboul A D,Wrobel F, et al. A simple method for assessing power devices sensitivity to SEEs in atmospheric environment. IEEE Trans Nucl Sci, 2013; 60: 2559–2566CrossRefGoogle Scholar
  14. 14.
    Warren K W, Wilkinson J D, Weller R A, et al. Predicting neutron induced soft error rates: evaluation of accelerated ground based test methods. In: Proceedings of IEEE International Reliability Physics Symposium, Phoenix, 2008. 473–477Google Scholar
  15. 15.
    Warren K M, Sierawski B D, Reed R A, et al. Monte-Carlo based on-orbit single event upset rate prediction for a radiation hardened by design latch. IEEE Trans Nucl Sci, 2007; 54: 2419–2425CrossRefGoogle Scholar
  16. 16.
    Warren K M, Weller R A, Sierawski B D, et al. Application of RADSAFE to model the single event upset response of a 0.25 µm CMOS SRAM. IEEE Trans Nucl Sci, 2007; 54: 898–903CrossRefGoogle Scholar
  17. 17.
    Warren K M, Sternberg A L, Weller R A, et al. Integrating circuit level simulation and Monte-Carlo radiation transport code for single event upset analysis in SEU hardened circuitry. IEEE Trans Nucl Sci, 2008; 55: 2886–2894CrossRefGoogle Scholar
  18. 18.
    Hubert G, Duzellier S, Inguimbert C, et al. Operational SER calculations on the SAC-C orbit using the multi-scales single event phenomena predictive platform. IEEE Trans Nucl Sci, 2009; 56: 3032–3042CrossRefGoogle Scholar
  19. 19.
    Petersen E L. Interpretation of heavy ion cross section measurements. IEEE Trans Nucl Sci, 1996; 43: 952–959CrossRefGoogle Scholar
  20. 20.
    Petersen E L. The SEU figure of merit and proton upset rate calculations. IEEE Trans Nucl Sci, 1998; 45: 2550–2562CrossRefGoogle Scholar
  21. 21.
    Roche P, Gasiot G, Uznanski S, et al. A commercial 65nm CMOS technology for space applications: heavy ion, proton and gamma test results and modeling. In: Proceedings of European Conference on Radiation and Its Effects on Components and Systems, Bruges, 2009. 456–464Google Scholar
  22. 22.
    Petersen E L, Shapiro P, Adams J H, et al. Calculation of cosmic-ray induced soft upsets and scaling in VLSI devices. IEEE Trans Nucl Sci, 1982; 29: 2055–2063CrossRefGoogle Scholar
  23. 23.
    Hubert G, Bourdarie S, Artola L, et al. Multi-scale modeling to investigate the single event effects for space missions. Acta Astronaut, 2011; 69: 526–536CrossRefGoogle Scholar
  24. 24.
    Hazucha P, Svensson C. Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Trans Nucl Sci, 2000; 47: 2586–2594CrossRefGoogle Scholar
  25. 25.
    Amusan O A, Massengill L W, Baze M P, et al. Single event upsets in deep-submicrometer technologies due to charge sharing. IEEE Trans Dev Mater Rel, 2008; 8: 582–589CrossRefGoogle Scholar
  26. 26.
    Giot D, Roche P, Gasiot G, et al. Multiple-bit upset analysis in 90 nm srams: heavy ions testing and 3d simulations. IEEE Trans Nucl Sci, 2007; 54: 904–911CrossRefGoogle Scholar

Copyright information

© Science China Press and Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Liang He
    • 1
    Email author
  • Hua Chen
    • 1
  • Peng Sun
    • 1
  • Xiaofei Jia
    • 2
  • Chongguang Dai
    • 1
  • Jing Liu
    • 1
  • Long Shao
    • 1
  • Zhaoqing Liu
    • 1
  1. 1.School of Advanced Materials and NanotechnologyXidian UniversityXi’anChina
  2. 2.School of Electronic and Information EngineeringAnkang UniversityAnkangChina

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