Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Low Cost Scan Test by Test Correlation Utilization

  • 20 Accesses

  • 1 Citations


Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.

This is a preview of subscription content, log in to check access.


  1. [1]

    Jas A, Touba N. Test vector decompression via cyclical scan chains and its application to testing core-based designs. In Proc. International Test Conference, Washington DC, USA, 1998, pp.458–464.

  2. [2]

    Chandra A, Chakrabarty K. System-on-a-chip test-data compression architectures based on Golomb codes. IEEE Trans. Computer-Aided Design, March 2001, 20(3): 355–368.

  3. [3]

    Bayraktaroglu I, Orailoglu A. Test volume and application time reduction through scan chain concealment. In Proc. Design Automation Conference, Las Vegas, NV, USA, 2001, pp.151–155.

  4. [4]

    Wunderlich H J, Gerstendorfer S. Minimized power consumption for scan based BIST. In Proc. International Test Conference, Atlantic City, NJ, USA, 1999, pp.85–94.

  5. [5]

    Whetsel L. Adapting scan architectures for low power operation. In Proc. International Test Conference, Atlantic City, NJ, USA, 2000, pp.863–872.

  6. [6]

    Sinanoglu O, Bayraktaroglu I, Orailoglu A. Scan power reduction through test data transition frequency analysis. In Proc. International Test Conference, Baltimore, MD, USA, 2002, pp.844–850.

  7. [7]

    Sinanoglu O, Orailoglu A. Modeling scan chain modifications for scan-in test power minimization. In Proc. International Test Conference, Charlotte, USA, 2003, pp.602–611.

  8. [8]

    Sinanoglu O, Orailoglu A. Aggressive test power reduction through test stimuli transformation. In Proc. International Conference on Computer Design, San Jose, USA, 2003, pp.542–547.

  9. [9]

    Jas A, Pouya B, Touba N. Virtual scan chains: A means for reducing scan length in cores. In Proc. VLSI Test Symposium, Montreal, Canada, 2000, pp.73–78.

  10. [10]

    Hamzaoglu I, Patel J H. Reducing test application time for full scan embedded cores. In Proc. International Symposium on Fault-Tolerant Computing, Madison, USA, 1999, pp.260–267.

  11. [11]

    Fujiwara H, Yamamoto A. Parity-scan design to reduce the cost of test application. IEEE Transactions on Computer-Aided Design, October 1993, 12(10): 1604–1611.

  12. [12]

    Garey M, Johnson D S. Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, 1979.

  13. [13]

    Brglez F, Fujiwara H. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In Proc. IEEE Int. Symp. Circuits and Systems, Kyoto, Japan, June 1985, 3(3): 785–794.

  14. [14]

    Brglez F, Bryan D, Kozminski K. Combinational Profiles of Sequential Benchmark Circuits. IEEE Int. Symp. Circuits and Systems, Portland, USA, May 1989, 14(2): 1929–1934.

  15. [15]

    Lee H K, Ha D S. On the generation of test patterns for combinational circuits. Technical Report 12–93, Department of Electrical Eng., Virginia Polytechnic Institute and State University.

Download references

Author information

Correspondence to Ozgur Sinanoglu.

Electronic supplementary material

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Sinanoglu, O. Low Cost Scan Test by Test Correlation Utilization. J Comput Sci Technol 22, 681–694 (2007). https://doi.org/10.1007/s11390-007-9089-4

Download citation


  • scan-based testing
  • test data compression
  • test correlation
  • scan architecture design