Journal of Computer Science and Technology

, Volume 21, Issue 6, pp 907–912 | Cite as

Test Time Minimization for Hybrid BIST of Core-Based Systems

  • Gert Jervan
  • Petru Eles
  • Zebo Peng
  • Raimund Ubar
  • Maksim Jenihhin
Short Paper


This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.


SoC self-test hybrid BIST 


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Copyright information

© Springer Science + Business Media, Inc. 2006

Authors and Affiliations

  • Gert Jervan
    • 1
    • 2
  • Petru Eles
    • 1
  • Zebo Peng
    • 1
  • Raimund Ubar
    • 2
  • Maksim Jenihhin
    • 2
  1. 1.Embedded Systems Laboratory (ESLAB)Linköping UniversitySweden
  2. 2.Department of Computer EngineeringTallinn University of TechnologyEstonia

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