Innovations in Systems and Software Engineering

, Volume 14, Issue 4, pp 245–262 | Cite as

Formal verification of SysML diagram using case studies of real-time system

  • Sajjad AliEmail author
Original Paper


System and software engineers use SysML models for the graphical modeling of the embedded systems. The SysML models are inadequate to express the discrete controllers with continuously evolving variables. The real-time constraints such as discrete and continuous dynamics are considered to be an important aspect in embedded systems. The lack of support of real-time aspect in SysML model can lead to inexplicit modeling of the embedded systems. The imprecise modeling could cause catastrophic results when an embedded system gets operational. In this paper, we propose hybrid automata-based semantics that supports the discrete and continuous behavior in upgraded SysML block diagram. The upgraded SysML block diagram is used for the modeling of the embedded system. Furthermore, we use model checker PRISM for the early design verification of upgraded SysML block diagram. Finally, we demonstrate the effectiveness of our proposed approach with the help of two case studies “temperature control system” and “water level control system”.


SysML Formal modeling Verification Embedded system PRISM Continuous stochastic logic (CSL) Model checker Continuous time Markov chain (CTMC) 



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Copyright information

© Springer-Verlag London Ltd., part of Springer Nature 2018

Authors and Affiliations

  1. 1.National University of Sciences and TechnologyIslamabadPakistan

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