Generating heterogeneous executable specifications in SystemC from UML/MARTE models

Original Paper

DOI: 10.1007/s11334-009-0105-4

Cite this article as:
Peñil, P., Medina, J., Posadas, H. et al. Innovations Syst Softw Eng (2010) 6: 65. doi:10.1007/s11334-009-0105-4

Abstract

Modeling and analysis of real-time embedded system is becoming an important area of research nowadays. In this context, the UML/MARTE profile has been introduced to support the specification, design, and verification stages in the development process. It provides a wide set of facilities to capture the information required in the refinement steps throughout the design flow. To carry out the actions involved in these design steps, MARTE-based tools and methodologies are required. This paper presents a methodology to automatically generate SystemC heterogeneous executable specifications from generic MARTE models. To generate these specifications, the information included in the MARTE models is extracted to discover the system structure and hierarchy. A subset of the concurrency and communication features of the MARTE profile is used for this purpose. Then, automatic generation of the executable specification is possible. The code implementing the corresponding behavior can be easily integrated into the executable model. This design methodology proposes a refinement flow in order to perform the design steps before deciding the final system implementation.

Keywords

UML MARTE SystemC Heterogeneity Models of computation and communication 

Copyright information

© Springer-Verlag London Limited 2009

Authors and Affiliations

  1. 1.Microelectronics Engineering GroupUniversidad de CantabriaSantanderSpain
  2. 2.Departamento de Electrónica y ComputadoresUniversidad de CantabriaSantanderSpain

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