A 1 V, 0.53 ns, 59 μW Current Comparator Using Standard 0.18 μm CMOS Technology

  • Fei YuEmail author
  • Lei Gao
  • Li Liu
  • Shuai Qian
  • Shuo Cai
  • Yun Song


This letter aim to propose a current comparator based on simple current mirror which use single amplifier to reduce input offset, the improving symmetry current comparator achieve lower propagation delay (0.53 ns at input current \(I = 10\,{\upmu }\)A) and lower power dissipation (59 \({\upmu }\)W at SS corner) by comparing proposed structure at the supply voltage of 1 V, circuit simulations are performed in cadence software and hspice for a 0.18 \({\upmu }\)m TSMC standard CMOS process.


Current comparator Current mirror Amplifier Propagation delay 



This work was supported by the National Natural Science Foundation of China under Grants 61504013, 61702052 and 61772087, and by the Natural Science Foundation of Hunan Province under Grants 2019JJ50648 and 2016jj2005, and by the Scientific Research Fund of Hunan Provincial Education Department under grants 18A137 and 16B212.


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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.School of Computer and Communication EngineeringChangsha University of Science and TechnologyChangshaChina

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