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High Rate APPS and Bi-APPS LDPC Codes Design with Low Error Floor and Large Girth

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Abstract

In this paper, two new methods to construct low-density parity-check (LDPC) codes with low error floor and large girth are proposed. The first one is APPS-LDPC codes based on Arithmetic Progression theory and cycle classification, whose girth is at least eight. Based on the designed APPS-LDPC codes, we further construct Bi-diagonal APPS-LDPC codes with column degree 4, whose circulant permutation matrix is combined by two shifted identity matrix. The designed APPS-LDPC code has 0.25 and 0.2 dB coding gain compared to partition-and-shift (PS)-LDPC code and progressive-edge-growth (PEG)-LDPC code. And the Bi-APPS-LDPC code has similar performance to T2 LDPC code in CCSDS standard, but its effective structure is more suitable for high throughput decoder implementation on FPGA. Both codes have less construction complexity than PS-LDPC code and PEG-LDPC code.

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Acknowledgements

The authors are grateful to the anonymous reviewers and the support of the National Science Foundation of China (No. 61501479). Meanwhile, the authors would like to thank Hua Zhou for his helpful discussions and comments on this paper.

Author information

Correspondence to Erbao Li.

Additional information

This work is supported by the National Natural Science Foundation of China (No. 61501479).

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Li, E., Dong, L. & Lei, J. High Rate APPS and Bi-APPS LDPC Codes Design with Low Error Floor and Large Girth. Wireless Pers Commun 100, 709–720 (2018). https://doi.org/10.1007/s11277-018-5342-0

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Keywords

  • LDPC codes
  • Cycles
  • Girth
  • Trapping sets
  • Error floor
  • Arithmetic Progression theory
  • Partition-and-shift LDPC codes