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, Volume 80, Issue 4, pp 1517–1533 | Cite as

Enhanced Power Gating Schemes for Low Leakage Power and Low Ground Bounce Noise in Design of Ring Oscillator

  • Sheetal Soni
  • Shyam Akashe
Article

Abstract

As the technology is emerging rapidly, the size of complex and large circuits is scaling towards nanometer scale. So, the increment can be seen in two critical sources of noise as leakage current and ground bounce. These are the two main design constraints of the circuit design. In this paper, a comparative analysis has been done to mitigate the effect of GBN during sleep to active mode transition and to design more noise immune circuit. Enhanced power gating schemes have been simulated and presented here which show very drastic reduction in leakage power and GBN. By using power gating scheme, GBN is greatly reduced to 93 %, 90 % reduced by diode based technique and 88 % reduced by using staggered phase scheme as compared to the base case when GBN is measured for different delay cells at 45 nm scale. A significant amount of leakage power has been reduced to 64 % by using power gating scheme, 75 % reduced by diode based technique and 78 % reduced by using staggered phase scheme as compared to the base case measured for different delay cells at 45 nm scale.

Keywords

Low Power Ground bound noise CMOS Ring oscillator 

Notes

Acknowledgments

The authors would like to thank ITM University and Cadence Pvt. Ltd, Bangalore for theis immense support and guidance.

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Research ScholarITMGwaliorIndia
  2. 2.Department of ECEITM UniversityGwaliorIndia

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