Wireless Personal Communications

, Volume 80, Issue 4, pp 1517–1533 | Cite as

Enhanced Power Gating Schemes for Low Leakage Power and Low Ground Bounce Noise in Design of Ring Oscillator

  • Sheetal Soni
  • Shyam Akashe


As the technology is emerging rapidly, the size of complex and large circuits is scaling towards nanometer scale. So, the increment can be seen in two critical sources of noise as leakage current and ground bounce. These are the two main design constraints of the circuit design. In this paper, a comparative analysis has been done to mitigate the effect of GBN during sleep to active mode transition and to design more noise immune circuit. Enhanced power gating schemes have been simulated and presented here which show very drastic reduction in leakage power and GBN. By using power gating scheme, GBN is greatly reduced to 93 %, 90 % reduced by diode based technique and 88 % reduced by using staggered phase scheme as compared to the base case when GBN is measured for different delay cells at 45 nm scale. A significant amount of leakage power has been reduced to 64 % by using power gating scheme, 75 % reduced by diode based technique and 78 % reduced by using staggered phase scheme as compared to the base case measured for different delay cells at 45 nm scale.


Low Power Ground bound noise CMOS Ring oscillator 



The authors would like to thank ITM University and Cadence Pvt. Ltd, Bangalore for theis immense support and guidance.


  1. 1.
    Design of low-voltage wide tuning range cmos multipass voltage-controlled ring oscillator by jie ren, dalhousie university halifax, nova scotia March 2011.Google Scholar
  2. 2.
    Chen, O. C., & Sheen, R. (2002). A power-efficient wide-range phase-locked loop. IEEE Journal of Solid State Circuits, 37(1), 51–62.CrossRefGoogle Scholar
  3. 3.
    Razavi, B. (1997). A 2-GHz 1.6-mW phase-locked loop. IEEE Journal Solid-State Circuits, 32, 730–735.CrossRefGoogle Scholar
  4. 4.
    Park, C. H., Kim, O., & Kim, B. (2001). A 1.8-GHz self-calibrated phase locked loop with precise I/Q matching. IEEE Journal Solid-State Circuits, 36, 777–783.CrossRefGoogle Scholar
  5. 5.
    Sun, L., & Kwasniewski, T. A. (2001). A 1.25-GHz 0.35- m monolithic CMOS PLL based on a multiphase ring oscillator. IEEE Journal Solid-State Circuits, 36, 910–916.CrossRefGoogle Scholar
  6. 6.
    Catli, B., & Haskell, M. M. (2008). A 0.5V 3.6/5.2 GHz CMOS multi-band VCO for ultra low-voltage wireless applications.IEEE International Symposium on Circuits and Systems, pp. 996–999, May 2008.Google Scholar
  7. 7.
    Chuang, Y.-H., Lee, S.-H., Jang, S.-L., Chao, J.-J., & Juang, M.-H. (2006). IEEE a ring-oscillator-based wide locking range frequency divider. IEEE Microwave and Wireless Components Letters, (16) 8, August 2006.Google Scholar
  8. 8.
    Yi, X., Do, M. A., Yeo, K. S., & Lim, W. M. (2011). Design of ring-oscillator-based injection-locked frequency dividers with single phase inputs. IEEE Microwave and Wireless Componds Letters, (21)10, October 2011.Google Scholar
  9. 9.
    Paula, L. S., Banpi, S., Fabris, E., & Susin, A. A. (2008). A wide band CMOS differential voltage-controlled ring oscillators, International.IEEE Northeast Workshop on Circuits and System Design, pp. 9–12, 2008, Jun. 2008Google Scholar
  10. 10.
    Eken Y. A. & Uyemura, J. P. (2004). A 5.9-GHz voltage-controlled ring oscillator in 0.18-m CMOS. IEEE Journal of Solid-State Circuits, 39 (1), January 2004.Google Scholar
  11. 11.
    Docking, S., & Sachdev, M. (2003). A method to derive an equation for the oscillation frequency of a ring oscillator. IEEE Transaction on Circuits and Systems- I: Fundamental Theory and Applications, 50(2), 259–264.CrossRefGoogle Scholar
  12. 12.
    Mollah, A.K.M. K., Rosales, R., Tabatabaei, S., Cicalo, J., & Ivanov, A., (2007) Fellow, IEEE Design of a tunable differential ring oscillator with short start-up and switching transients. IEEE Transactions on Circuits and Systems—I: Regular Papers, 54 (12), December 2007.Google Scholar
  13. 13.
    Herzel, F., & Razavi, B. (1999) .A study of oscillator jitter due to supply and substrate noise. IEEE Transactions on Circuits and Systems–II: Analog and Digital Signal Processing, 46, (1), January 1999.Google Scholar
  14. 14.
    Brownlee, M., Hanumolu, P. K., Moon, U. K., & Mayaram, K. (2004). The effect of power supply noise on ring oscillator phase noise. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS), pp. 225–228, June 2004.Google Scholar
  15. 15.
    Deen, M.J., Kazemeini, M.H., & Naseh, S. (2003).Performance characteristics of an ultra-low power VCO.International Symposiumon Circuits and Systems, pp. 697–700, May 2003.Google Scholar
  16. 16.
    Roy, K., & Prasad, S. C. (2002). Low power CMOS circuit design. India: Wiely Pvt Ltd.Google Scholar
  17. 17.
    Doris, B., Ieong, M., Kanarsky, T., Zhang, Y., Roy, R.A., Dokumaci, O., Ren, Z., Jamin, F.-F., Shi, L., Natzle, W., Huang, H.-J., Mezzapelle, J., Mocuta, A., Womack, S., Gribelyuk, M., Jones, E. C., Miller, R.J., Wong, H.-S. P., & Haensch, W. (2002). Extreme scaling with ultra-thin Si channel MOSFETs, IEDM Tech. Dig., pp. 267–270Google Scholar
  18. 18.
    Skotnicki, T., Fenouillet-Beranger, C., Gallon, C., Boeuf, F., Monfray, S., Payet, F., et al. (2008). Innovative materials, devices, andCMOS technologies for low-power mobile multimedia. IEEE Transaction Electron Device, 55, 96–130.CrossRefGoogle Scholar
  19. 19.
    Miyashita, T., Ikeda, K., Kim, Y.S., Yamamoto, T., Sambonsugi, Y., Ochimizu, H., et al. (2007). High-performance and low-power bulk logic platform utilizing FET specific multiple-stressors with highly enhanced strain and full-porous low-k interconnects for 45-nm CMOS technology. In: Proceedings of the IEEE International Electron Devices Meeting, (IEDM 2007), Washington, DC, USA, pp. 251–254, 10–12 December 2007.Google Scholar
  20. 20.
    Badaroglu, M., Van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Gielen, G. G. E., et al. (2002). Methodology and experimental verifications for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE Journal Solid-State Circuits, 37, 1383–1395.CrossRefGoogle Scholar
  21. 21.
    Xu, M., Su, D.K., Shaeffer, D.K., Lee, T.H., & Wooley, B.A. (2000) .Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver, proceedings of IEEE conference on custom integrated circuit conference (CICC), pp. 353–356, May 2000.Google Scholar
  22. 22.
    Park, J. C., & Mooney, V. J. (2006). Sleepy stack leakage reduction. IEEE transactions on very large scale integration (vlsi) systems, 14(1). november 2006.Google Scholar
  23. 23.
    Kim, S., et al. (2003) .Understanding and minimizing ground bounce during mode transition of power gating structure. In: Proc. Int. Symp. Low-Power Electron. Des., pp. 22–25, Augest 2003.Google Scholar
  24. 24.
    Agarwal, K., Deogun, H., Sylvester, D., & Nowka, K. (2006) Power gating with multiple sleep modes. In: Proc. Int. Symp. Quality Electron. Des., pp. 633–637, Mar. 2006.Google Scholar
  25. 25.
    Kim, S., Choi, C. J., Jeong, D. K., Kosonocky, S. V., & Park, S. B. (2008). Reducing ground-bounce noise and stabilizing the data-retention voltage of power-gating structures.IEEE transactions on Electron Devices, 55(1), January 2008.Google Scholar
  26. 26.
    Akl, C. J., Ayoubi, R. A., & Bayoumi, M. A. (2009) An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition, 10th International Symposium on Quality of Electronic Design, pp. 116–119, 2009.Google Scholar
  27. 27.
    He, K., Luo, R., & Wang, Y. (2007). A Power Gating Scheme for Ground Bounce Reduction During Mode Transition. In: ICCD07, pp. 388–394, 2007.Google Scholar
  28. 28.
    Kratyuk, V., Vytyaz, I., Moon, U-K., & Mayaram, K. (2005). Analysis of supply and ground noise sensitivity in ring and LC oscillators. IEEE international symposium on Circuit & Systems (ISCAS), 6, 5986–5989.Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Research ScholarITMGwaliorIndia
  2. 2.Department of ECEITM UniversityGwaliorIndia

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