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, Volume 71, Issue 1, pp 123–136 | Cite as

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology

  • Shyam Akashe
  • Sanjay Sharma


In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved.


CMOS Gate leakage current Sub threshold current Voltage level switch SRAM Stand-by power 


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  1. 1.
    Zhang L., Wu C., Mao L., Zheng J. (2012) Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process. Micro & Nano Letters 7(2): 171–173CrossRefGoogle Scholar
  2. 2.
    Mutoh, S., Shigematsu, S., Matsuya, Y., Fukuda, H., & Yamada, J. (1996). A 1-V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application. In IEEE international solid-state circuits conference digest of technical papers (pp. 168–169).Google Scholar
  3. 3.
    Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., et al. (1996). A 0.9-V, 150-MHz, 10-mW, 4 mm 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE Journal of Solid-State Circuits, 31(11), 1770–1779.Google Scholar
  4. 4.
    Van der Meer, P. R., van Staveren, A., & van Roermund, A. H. M. (2000). Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: Smart series switch. In Proceedings of IEEE international symposium on circuits and systems (pp. 1–4). Geneva.Google Scholar
  5. 5.
    Enomoto, T., Oka, Y., Shikano, H., & Harada, T. (2002). A self-controllable voltage-level (SVL) circuit for low-power, high-speed CMOS circuits. In Proceedings of European solid-state circuits conference (pp. 411–414). Firenze, Italy.Google Scholar
  6. 6.
    Birla S., Singh R. K., Pattanaik M. (2011) Static noise margin analysis of various SRAM topologies. IACSIT International Journal of Engineering and Technology 3(3): 304–309Google Scholar
  7. 7.
    Birla, S., Shukla, N., Pattanaik, M., & Singh, R. K. (2010). Device and circuit design challenges for low leakage SRAM for ultra low power applications. Canadian Journal on Electrical and Electronics Engineering, 1(7), 11–15, 156–167.Google Scholar
  8. 8.
    Agarwal, A., & Roy, K. (2003). A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. In ISPLED’03 (pp. 18–21). Seoul, Korea.Google Scholar
  9. 9.
    Razavipour G., Afzali-Kusha A., Pedram M. (2009) Design and analysis of two low-power SRAM cell structures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17(10): 1551–1555CrossRefGoogle Scholar
  10. 10.
    Kim N., Flautner K., Blaauw D., Mudge T. (2004) Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Transactions on VLSI Systems 12(2): 167–184CrossRefGoogle Scholar
  11. 11.
    Agarwal, A., Li, H., & Roy, K. (2002). DRG-cache: A data retention gated-ground cache for low power. In Proceedings of the 39th design automation conference (pp. 473–478).Google Scholar
  12. 12.
    Hamzaoglu, F., Ye, Y., Keshavarzi, A., Zhang, K., Narendra, S., Borkar, S., Stan, M., & De, V. (2000). Dual Vr SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13um technology generation. In Proceedings of the 2000 international symposium on low power electronics and design (pp. 15–19).Google Scholar
  13. 13.
    Enomoto T., Oka Y., Shikano H. (2003) Self-controllable voltage level (SVL) circuit and its low-power high- speed CMOS circuit applications. IEEE Journal of Solid State Circuits 38(7): 1220–1226CrossRefGoogle Scholar
  14. 14.
    Hamzaoglu, F., & Stan, M. (2002). Circuit-level techniques to control gate leakage for sub-100 nm CMOS. In ISPLED’02 (pp. 60-63). Monterey, CA, USA.Google Scholar
  15. 15.
    Mohanty S., Singh J., Kougians E., Pradhan D. (2012) Statistical DOE-ILP based power-performance-process (P3) optimization of nano- CMOS SRAM INTIGRATION. The VLSI Journal 45: 33–45CrossRefGoogle Scholar
  16. 16.
    Islam A., Hassan M. (2011) Variability analysis of 6T and 7T SRAM cell in Sub-45 nm technology. IIUM Engineering Journal 12(1): 13–30Google Scholar
  17. 17.
    Chung Y., Lee D. (2010) Differential-read symmetrical 8T SRAM bit-cell with enhanced data stability. Electronics Letters 46(18): 1258–1260MathSciNetCrossRefGoogle Scholar
  18. 18.
    Goel A., Sharma R. K., Gupta A. K. (2012) Process variations aware area efficient negative bit-line voltage scheme of improving write ability of SRAM in nanometer technologies. IET Journal 6(1): 45–51Google Scholar
  19. 19.
    Ho Y., Chang C., Su C. (2012) Design a subthreshold-supply bootstrapped CMOS inverter based on an active leakage-current reduction technique. IEEE Transactions on Circuits and Systems 59(1): 55–59CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC. 2012

Authors and Affiliations

  1. 1.Department of Electronics & Communication EngineeringThapar UniversityPatialaIndia

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