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A fault-tolerant and congestion-aware architecture for wireless networks-on-chip

  • Seyed Hassan Mortazavi
  • Reza Akbar
  • Farshad SafaeiEmail author
  • Amin Rezaei
Article
  • 19 Downloads

Abstract

The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone than the conventional ones not only because of their implementation complexities but also due to their relatively high utilization. In this paper, a new topology is presented to enhance the network reliability, and then a novel routing algorithm is proposed to tolerate both intermittent and permanent faults on wireless hubs. In the proposed approach, once a wireless hub becomes faulty, the best alternative adjustment hub will be indicated and all the packets that have high average hop-count are routed through this alternative hub. In comparison with the state-of-the-art works, the proposed approach shows significant improvements in terms of robustness, congestion management, and resilience.

Keywords

Network-on-chip Hybrid wireless network-on-chip Many-core system-on-chip Reliability Robustness Congestion control management 

Notes

References

  1. 1.
    Dally, W., & Towles, B. (2001). Route packets, not wires: On-chip interconnection networks. In Proceedings of the design automation conference (pp. 684–689), CA, USA.Google Scholar
  2. 2.
    Rezaei, A., Zhao, D., Daneshtalab, M., & Zhou, H. (2017). Multi-objective task mapping approach for wireless NoC in dark silicon age. In International conference on parallel, distributed and network-based processing (PDP) (pp. 589–592), St. Petersburg, Russia.Google Scholar
  3. 3.
    Chen, Y. Y., Chang, E. J., Hsin, H. K., Chen, K., & Wu, A. (2017). Path-diversity-aware fault-tolerant routing algorithm for network-on-chip. IEEE Transactions on Parallel and Distributed Systems, 28(3), 838–849.CrossRefGoogle Scholar
  4. 4.
    Akbar, R., & Safaei, F. (2018). A novel adaptive congestion-aware and load-balanced routing algorithm in networks-on-chip. Computers & Electrical Engineering, 71, 60–76.CrossRefGoogle Scholar
  5. 5.
    Pavlidis, V. F., & Friedman, E. G. (2007). 3-D topologies for networks-on-chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(10), 1081–1090.CrossRefGoogle Scholar
  6. 6.
    Feero, B. S., & Pande, P. P. (2009). Networks-on-chip in a threedimensional environment: A performance evaluation. IEEE Transactions on Computer, 58(1), 32–45.CrossRefzbMATHGoogle Scholar
  7. 7.
    Rezaei, S. H. S., Modarressi, M., Aminabadi, R. Y., & Daneshtalab, M. (2016). Fault-tolerant 3-D network-on-chip design using dynamic link sharing. In Design, automation & test in Europe conference & exhibition (DATE) (pp. 1195–1200), Dresden, Germany.Google Scholar
  8. 8.
    Salamat, R., Khayambashi, M., Ebrahimi, M., & Bagherzadeh, N. (2018). LEAD: An adaptive 3D-NoC routing algorithm with queuing-theory based analytical verification. IEEE Transactions on Computers, 67(8), 1153–1166.MathSciNetzbMATHGoogle Scholar
  9. 9.
    Shacham, A., Bergman, K., & Carloni, L. P. (2008). Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Transactions on Computers, 57(9), 1246–1260.MathSciNetCrossRefGoogle Scholar
  10. 10.
    Pan, Y., Kumar, P., Kim, J., Memik, G., Zhang, Y., & Choudhary, A. (2009). Firefly: Illuminating future network-on-chip with nanophotonics. In Proceedings of the annual international symposium on computer architecture (pp. 429–440), Texas, USA.Google Scholar
  11. 11.
    Chang, M. F., Cong, J., Kaplan, A., Naik, M., Reinman, G., Socher, E., et al. (2008). CMP network-on-chip overlaid with multi-band RF-interconnect. In High performance computer architecture (HPCA) (pp. 191–202), Salt Lake City, UT, USA.Google Scholar
  12. 12.
    Ganguly, A., Chang, K., Deb, S., Pande, P. P., Belzer, B., & Teuscher, C. (2011). Scalable hybrid wireless network-on-chip architectures for multicore systems. IEEE Transactions on Computers, 60(10), 1485–1502.MathSciNetCrossRefzbMATHGoogle Scholar
  13. 13.
    Deb, S., Ganguly, A., Pande, P. P., Belzer, B., & Heo, D. (2012). Wireless NoC as interconnection backbone for multicore chips: Promises and challenges. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2(2), 228–239.CrossRefGoogle Scholar
  14. 14.
    Deb, S., Chang, K., Yu, X., Sah, S. P., Cosic, M., Ganguly, A., et al. (2013). Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects. IEEE Transactions on Computers, 62(12), 2382–2396.MathSciNetCrossRefGoogle Scholar
  15. 15.
    Chang, K., Deb, S., Ganguly, A., Yu, X., Sah, S. P., Pande, P. P., et al. (2012). Performance evaluation and design trade-offs for wireless network-on-chip architectures. ACM Journal on Emerging Technologies in Computing Systems (JETC), 8(3), 23.Google Scholar
  16. 16.
    Wettin, P., Murray, J., Kim, R., Yu, X., Pande, P. P., & Heo, D. (2014). Performance evaluation of wireless NoCs in presence of irregular network routing strategies. In Design, automation and test in Europe conference and exhibition (DATE) (pp. 1–6), Dresden, Germany.Google Scholar
  17. 17.
    Dehghani, A., & Jamshidi, K. (2016). A novel approach to optimize fault-tolerant hybrid wireless network-on-chip architectures. ACM Journal on Emerging Technologies in Computing Systems (JETC), 12(4), 45.Google Scholar
  18. 18.
    Dehghani, A., & Jamshidi, K. (2015). A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms. The Journal of Supercomputing, 71(8), 3116–3148.CrossRefGoogle Scholar
  19. 19.
    Ogras, U. Y., & Marculescu, R. (2006). It’s a small world after all: NoC performance optimization via long-range link insertion. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(7), 693–706.CrossRefGoogle Scholar
  20. 20.
    Bahrami, B., Jamali, M. A. J., & Saeidi, S. (2017). A hierarchical architecture based on traveling salesman problem for hybrid wireless network-on-chip. Wireless Networks, 1, 1–14.Google Scholar
  21. 21.
    Wang, C., Hu, W. H., & Bagherzadeh, N. (2012). A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. Microprocessors and Microsystems, 36(7), 555–570.CrossRefGoogle Scholar
  22. 22.
    Hu, H. W., Wang, C., & Bagherzadeh, N. (2015). Design and analysis of a mesh-based wireless network-on-chip. The Journal of Supercomputing, 71(8), 2830–2846.CrossRefGoogle Scholar
  23. 23.
    Rezaei, A., Safaei, F., Daneshtalab, M., & Tenhunen, H. (2014). HiWA: A hierarchical wireless network-on-chip architecture. In: Conference on high performance computing & simulation (HPCS) (pp. 499–505), Bologna, Italy.Google Scholar
  24. 24.
    Rezaei, A., Daneshtalab, M., Safaei, F., & Zhao, D. (2016). Hierarchical approach for hybrid wireless network-on-chip in many-core era. Computers & Electrical Engineering, 51, 225–234.CrossRefGoogle Scholar
  25. 25.
    Rezaei, A., Daneshtalab, M., & Zhao, D. (2017). CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era. Microprocessors and Microsystems, 52, 23–33.CrossRefGoogle Scholar
  26. 26.
    Zhao, D., & Wang, Y. (2008). SD-MAC: Design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Transactions on Computers, 57(9), 1230–1245.MathSciNetCrossRefzbMATHGoogle Scholar
  27. 27.
    Afsharmazayejani, R., Yazdanpanah, F., Rezaei, A., Alaei, M., & Daneshtalab, M. (2018). HoneyWiN: Novel honeycomb-based wireless NoC architecture in many-core era. In International symposium on applied reconfigurable computing (ARC) (pp. 304–316).Google Scholar
  28. 28.
    Kumar, A., Peh, L. S., & Jha, N. K. (2008). Token flow control. In Proceedings of the international symposium on microarchitecture (pp. 342–353).Google Scholar
  29. 29.
    Palesi, M., Collotta, M., Mineo, A., & Catania, V. (2015). An efficient radio access control mechanism for wireless network-on-chip architectures. Journal of Low Power Electronics and Applications, 5(2), 38–56.CrossRefGoogle Scholar
  30. 30.
    Ganguly, A., Wettin, P., Chang, K., & Pande, P. (2011). Complex network inspired fault-tolerant NoC architectures with wireless links. In International symposium on networks on chip (NoCS) (pp. 169–176), Pittsburgh, Pennsylvania.Google Scholar
  31. 31.
    Catania, V., Mineo, A., Monteleone, S., Palesi, M., & Patti, D. (2016). Cycle-accurate network on chip simulation with noxim. ACM Transactions on Modeling and Computer Simulation (TOMACS), 27(1), 4.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Seyed Hassan Mortazavi
    • 1
  • Reza Akbar
    • 1
  • Farshad Safaei
    • 1
    Email author
  • Amin Rezaei
    • 2
  1. 1.Faculty of Computer Science and EngineeringShahid Beheshti University G.C.Evin, TehranIran
  2. 2.Department of Electrical Engineering and Computer ScienceNorthwestern University (NU)EvanstonUSA

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