A fault-tolerant and congestion-aware architecture for wireless networks-on-chip

  • Seyed Hassan Mortazavi
  • Reza Akbar
  • Farshad SafaeiEmail author
  • Amin Rezaei


The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone than the conventional ones not only because of their implementation complexities but also due to their relatively high utilization. In this paper, a new topology is presented to enhance the network reliability, and then a novel routing algorithm is proposed to tolerate both intermittent and permanent faults on wireless hubs. In the proposed approach, once a wireless hub becomes faulty, the best alternative adjustment hub will be indicated and all the packets that have high average hop-count are routed through this alternative hub. In comparison with the state-of-the-art works, the proposed approach shows significant improvements in terms of robustness, congestion management, and resilience.


Network-on-chip Hybrid wireless network-on-chip Many-core system-on-chip Reliability Robustness Congestion control management 



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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Seyed Hassan Mortazavi
    • 1
  • Reza Akbar
    • 1
  • Farshad Safaei
    • 1
    Email author
  • Amin Rezaei
    • 2
  1. 1.Faculty of Computer Science and EngineeringShahid Beheshti University G.C.Evin, TehranIran
  2. 2.Department of Electrical Engineering and Computer ScienceNorthwestern University (NU)EvanstonUSA

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