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SDMPSoC: Software-Defined MPSoC for FPGAs

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Nowadays, heterogeneous Multiprocessor Systems-on-Chip are often used for a wide variety of applications such as image and signal processing due to the high computational power. However, the programming and designing of such systems requires a high expertise in hardware as well as software. This is in contrast to a short time-to-market which is essential for the industry. As a result, a crucial software productivity gap emerges. This work presents SDMPSoC which is an automatic development environment for heterogeneous and FPGA-based MPSoCs. Based on an MPI program, a heterogeneous MPSoC for FPGAs consisting of an arbitrary number of MicroBlaze processors and hardware modules is generated. Each process of the MPI program is executed by a MicroBlaze processor or a hardware module which can be selected using constraints. Furthermore, every MicroBlaze processor can be optimized by hardware modules that executes application-specific operations. All hardware modules can be easily programmed in the MPI program and are synthesized using high-level synthesis. Functions of the MPI program can be selected by pragmas for hardware modules that are connected to a MicroBlaze processor. A process of the MPI program can be selected by constraints for a hardware module that is a PE without MicroBlaze processor. To evaluate the environment in terms of scalability, performance and area, several use cases have been implemented on a Xilinx Zynq SoC. The development phase and programming of heterogeneous MPSoCs are significantly simplified by the automatic development environment.

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  1. 1.

    Nouri, S., Hussain, W., Nurmi, J. (2015). Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array. 2015 Conference on design and architectures for signal and image processing (DASIP), Krakow, pp. 1–8.

  2. 2.

    Wang, C., Li, X., Chen, Y., Zhang, Y., Diessel, O., Zhou, X. (2017). Service-Oriented Architecture on FPGA-Based MPSoC. IEEE Transactions on Parallel and Distributed Systems, 28(10), 2993–3006.

  3. 3.

    Rettkowski, J., & Göhringer, D. (2018). High-Level Synthesis of Software-defined MPSoCs 2018. In: Proc of the 14th international symposium on reconfigurable computing architectures, tools and applications (ARC), Santorini, Greece.

  4. 4.

    Wächter, E.W., Lucas, C., Carara amd, E.A., Moraes, F.G. (2012). An open-source framework for heterogeneous MPSoC generation. 2012 VIII Southern conference on programmable logic, Bento Goncalves, pp. 1–6.

  5. 5.

    Pilato, C., & Ferrandi, F. (2013). Bambu: A modular framework for the high level synthesis of memory-intensive applications. 2013 23rd international conference on field programmable logic and applications, Porto, pp. 1–4.

  6. 6.

    Xilinx. (2017). Vivado design suite user guide – high level synthesis. UG902 (v2017.1), www.xilinx.com.

  7. 7.

    Canis, A., Choi, J., Fort, B., Syrowik, B., Lian, R.L., Chen, Y.T., Hsiao, H., Goeders, J., Brown, S., Anderson, J.H. (2016). LegUp high-level synthesis. Chapter in FPGAs for Software Engineers, Springer.

  8. 8.

    Mori, J.Y., Werner, A., Fricke, F., Hübner, M. (2017). A rapid prototyping method to reduce the design time in commercial high-level synthesis tools. UG902 (v2017.1), www.xilinx.com.

  9. 9.

    Xilinx. (2017). SDSoC Development Environment - User Guide. UG1027 (v2017.1), www.xilinx.com.

  10. 10.

    Bezati, E., Casale-Brunet, S., Mattavelli, M., Janneck, J.W. (2016). High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. 2016 International conference on embedded computer systems: Architectures, modeling and simulation (SAMOS), pp. 227–234.

  11. 11.

    Xilinx. (2017). Zynq-7000 all programmable SoC – technical reference manual. UG585 (v1.11), www.xilinx.com.

  12. 12.

    Xilinx. (2017). Zynq Ultrascale+ MPSoC – Technical reference manual. UG1085 (v1.5), www.xilinx.com.

  13. 13.

    Suneeta, R. (2017). RamSagar Srinivasan SoC implementation of three phase BLDC motor using Microblaze soft IP core. 2017 International conference on computer, communications and electronics (Comptelix), Jaipur, pp. 360–364.

  14. 14.

    Farhat, W., Faiedh, H., Souani, C., Besbes, K. (2015). Embedded system for road sign detection using MicroBlaze. 2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), Mahdia, pp. 1–5.

  15. 15.

    Khanzadi, H., Savaria, Y., David, J.P. (2017). A data driven CGRA Overlay Architecture with embedded processors. 2017 15th IEEE international new circuits and systems conference (NEWCAS), Strasbourg, pp. 269–272.

  16. 16.

    Rettkowski, J., & Göhringer, D. (2017). Application-specific processing using high-level synthesis for networks-on-chip. 2017 International conference on reconfigurable computing and FPGAs (ReConFig), Cancun.

  17. 17.

    Peh, L., & Dally, W.J. (2000). Flit-reservation flow control. Proceedings 6th international symposium on high-performance computer architecture. HPCA-6 (Cat. No.PR00550), Touluse, pp. 73–84.

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Correspondence to Jens Rettkowski.

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Rettkowski, J., Göhringer, D. SDMPSoC: Software-Defined MPSoC for FPGAs. J Sign Process Syst (2019). https://doi.org/10.1007/s11265-019-01462-9

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  • Software-defined MPSoC
  • Vivado HLS
  • FPGA
  • MPSoC