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Journal of Signal Processing Systems

, Volume 91, Issue 1, pp 75–91 | Cite as

Modeling and Analysis of FPGA Accelerators for Real-Time Streaming Video Processing in the Healthcare Domain

  • Steven van der VlugtEmail author
  • Hadi Alizadeh Ara
  • Rob de Jong
  • Martijn Hendriks
  • Ruben Guerra Marin
  • Marc Geilen
  • Dip Goswami
Article
  • 86 Downloads

Abstract

Complex real-time video processing applications with strict throughput constraints are commonly found in a typical healthcare application. The video processing chain is implemented as Field-Programmable Gate Array (FPGA) accelerators (processing blocks) communicating through a number of First-In First-Out (FIFO) buffers. The FIFO buffers are made out of Block RAM (BRAM) and limited in availability. Therefore, a key design question is the optimal sizes of the FIFO buffers with respect to the throughput constraint. In this paper, we use model-driven analysis and detailed hardware level simulation to address the question of buffer dimensioning in an efficient way. Using a Cyclo-Static Dataflow (CSDF) model and an optimization method, we identify and optimize the FIFO buffers. The results are confirmed using a detailed hardware level simulation and validated by comparison with VHDL simulations. The technique is illustrated on a use case from Philips Healthcare Image Guided Therapy (IGT) on the imaging pipeline of an Interventional X-Ray (i XR) system.

Keywords

Throughput Latency Buffer sizing Optimized hardware synthesis 

Notes

Acknowledgements

This work has been supported by the ALMARVI European Artemis project nr. 621439.

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Philips HealthcareBestThe Netherlands
  2. 2.TOPIC Embedded SystemsBestThe Netherlands
  3. 3.Eindhoven University of TechnologyEindhovenThe Netherlands
  4. 4.ESI (TNO)EindhovenThe Netherlands

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