This paper presents novel architectures for linear-phase FIR digital filters using stochastic computing. Stochastic computing systems require fewer logic gates and are inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. Compared to direct-form linear-phase FIR filters, linear-phase lattice filters require twice the number of multipliers but the same number of adders. The hardware complexities of stochastic implementations of linear-phase FIR filters for direct-form and lattice structures are comparable. This is because multipliers do not require any more area than adders. Two stochastic implementations of lattice FIR filters are proposed in this paper. Using speech signals from ICA ’99 Synthetic Benchmarks, it is shown that, for linear-phase FIR filters, the signal-to-error ratios of stochastic direct-form and stochastic lattice filters are abou the same.
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This research was supported by the National Science Foundation under grant number CCF-1319107.
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Liu, Y., Parhi, K.K. Linear-Phase Lattice FIR Digital Filter Architectures Using Stochastic Logic. J Sign Process Syst 90, 791–803 (2018). https://doi.org/10.1007/s11265-017-1224-z
- Stochastic computing
- Stochastic logic
- FIR digital filter
- Lattice structure
- Linear-phase FIR filters
- Hardware complexity