This paper presents a selectable discrete-voltage output and fast-settling low-dropout regulator (LDO) by using half digitally-assistant voltage accelerator. The transition response time within reference switching and transient load regulation is significantly reduced by utilizing the discrete-voltage control technique and the half digitally-assistant voltage accelerator. The proposed LDO regulator provides two selectable discrete-voltage outputs of 2.8 V and 1.8 V by using the discrete-voltage control technique. The settling time is reduced by utilizing the half digitally-assistant voltage accelerator when the output voltage is switching. Furthermore, the new comparator architecture is proposed to avoid large under−/over-shoot voltage of the LDO output. According to the experimental results, the settling time of the proposed LDO regulator can be significantly reduced from 4.2 ms to 14.892 μs. Moreover, the discrete-voltage control unit and the half digitally-assistant voltage accelerator of the proposed LDO regulator consume only 0.11 mW under a load current of 100 mA. The figure of merit (FOM) of the proposed LDO regulator is improved by over 20 %, in comparison to previous works.
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The authors would like to thank the National Chip Implementation Center and National Science Council, Taiwan, for fabricating this chip and supporting this work, respectively.
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Yang, W., Hong, M. & Shen, J.M. A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator. J Sign Process Syst 89, 347–362 (2017). https://doi.org/10.1007/s11265-016-1205-7
- Low-dropout regulator
- Discrete-voltage control unit
- Half digitally-assistant voltage accelerator
- New comparator architecture