A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators
Images are often corrupted with noise during the image acquisition and transmission stage. Here, we propose a novel approach for the reduction of random-valued impulse noise in images and its hardware implementation on various state-of-the-art FPGAs. The presented algorithm consists of two stages in which the first stage detects whether pixels have been corrupted by impulse noise and the second stage performs a filtering operation on the detected noisy pixels. The human visual system is sensitive to the presence of edges in any image therefore the filtering stage consists of an edge preserving median filter which performs the filtering operation while preserving the underlying fine image features. Experimentally, it has been found that the proposed scheme yields a better Peak Signal-to-Noise Ratio (PSNR) compared to other existing median-based impulse noise filtering schemes. The algorithm is implemented using the high-level synthesis tool PARO as a highly parallel and deeply pipelined hardware design that simultaneously exploits loop level as well as instruction level parallelism with a very short latency of only few milliseconds for 16 bit images of size 512 × 512 pixels.
KeywordsFPGA Image denoising Noise detection Parallel architecture Random-valued impulse noise
- 1.The Concise Encyclopedia of Statistics. Springer, New York (2008).Google Scholar
- 3.Altera Corp (2013). Altera SDK for OpenCL Programming Guide.Google Scholar
- 4.Arvind, N.R. (2008). Hands-on Introduction to Bluespec System Verilog (BSV). In 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design, 2008. MEMOCODE 2008, pp 205–206. doi:10.1109/MEMCOD.2008.4547713.
- 5.Bhadouria, V.S., & Ghoshal D. (2015). A study on genetic expression programming-based approach for impulse noise reduction in images. Signal, Image and Video Processing pp 1–10, doi:10.1007/s11760-015-0780-6.
- 7.Calypto Design Systems Inc (2012). Calypto Product Family Datasheet.Google Scholar
- 12.Feautrier P., & Lengauer C. (2011). Polyhedron model. In Padua DA (ed) Encyclopedia of Parallel Computing, Springer, pp 1581–1592. doi:10.1007/978-0-387-09766-4_502.
- 14.Gonzalez, R.C., & Woods, R.E. (2002). Digital image processing. Engle-wood Cliffs: Prentice-Hall.Google Scholar
- 15.Gupta, S., Dutt, N., Gupta, R., & Nicolau, A. (2003). SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations. In Proceedings of the 16th International Conference on VLSI Design, pp 461–466.Google Scholar
- 16.Hannig, F. (2009). Scheduling techniques for high-throughput loop accelerators. Dissertation, University of Erlangen-Nuremberg, Germany, Verlag Dr Hut, Munich, Germany.Google Scholar
- 17.Hannig, F., Ruckdeschel, H., Dutta, H., & Teich, J. (2008). In PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing (ARC), Springer, Lecture Notes in Computer Science (LNCS), vol 4943, pp 287–293. doi:10.1007/978-3-540-78610-8_30.
- 22.Ma, Z., He, K., Wei, Y., Sun, J., & Wu, E. (2013). Constant time weighted median filtering for stereo matching and beyond. In Computer vision (ICCV), 2013 IEEE International Conference on, IEEE, pp 49-56.Google Scholar
- 23.Matsubara T., Moshnyaga V.G., & Hashimoto K. (2010). A fpga implementation of low-complexity noise removal. In 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010, IEEE, pp 255–258.Google Scholar
- 24.Petrovic, N., & Crnojevic, V. (2008). Universal impulse noise filter based on genetic programming. IEEE Transactions on Image Processing, 17(7). doi:10.1109/TIP.2008.924388.
- 26.Schmid, M., Hannig, F., Tanase, A., & Teich, J. (2014). High-level synthesis revised – Generation of FPGA accelerators from a domain-specific language using the polyhedron model. In Parallel Computing: Accelerating Computational Science and Engineering (CSE), Advances in Parallel Computing, vol 25, IOS Press, Amsterdam, The Netherlands, pp 497–506. doi:10.3233/978-1-61499-381-0-497.
- 31.Xilinx Inc (2013). Vivado Design Suite User Guide - High-Level synthesis.Google Scholar
- 34.Yagou, H., Ohtake, Y., & Belyaev, A. (2002). Mesh smoothing via mean and median filtering applied to face normals. In Geometric Modeling and Processing, 2002. Proceedings, pp 124–131. doi:10.1109/GMAP.2002.1027503.
- 35.Yang, Q., Ahuja, N., & Tan, K.H. (2014). Constant time median and bilateral filtering. International Journal of Computer Vision, 1–12.Google Scholar
- 37.Zhang, Q., Xu, L., & Jia, J. (2014). 100+ times faster weighted median filter (wmf). In Computer Vision and Pattern Recognition (CVPR), 2014 IEEE Conference on, pp 2830–2837. doi:10.1109/CVPR.2014.362.