Journal of Signal Processing Systems

, Volume 90, Issue 5, pp 675–685 | Cite as

Fast Low-Complexity Decoders for Low-Rate Polar Codes

  • Pascal GiardEmail author
  • Alexios Balatsoukas-Stimming
  • Gabi Sarkis
  • Claude Thibeault
  • Warren J. Gross


Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommodate low-rate codes. More constituent codes are recognized in the updated algorithm and dedicated hardware is added to efficiently decode these new constituent codes. We also alter the polar code construction to further decrease the latency and increase the throughput with little to no noticeable effect on error-correction performance. Rate-flexible decoders for polar codes of length 1024 and 2048 are implemented on FPGA. Over the previous work, they are shown to have from 22 % to 28 % lower latency and 26 % to 34 % greater throughput when decoding low-rate codes. On 65 nm ASIC CMOS technology, the proposed decoder for a (1024, 512) polar code is shown to compare favorably against the state-of-the-art ASIC decoders. With a clock frequency of 400 MHz and a supply voltage of 0.8 V, it has a latency of 0.41 μs and an area efficiency of 1.8 Gbps/mm 2 for an energy efficiency of 77 pJ/info. bit. At 600 MHz with a supply of 1 V, the latency is reduced to 0.27 μs and the area efficiency increased to 2.7 Gbps/mm 2 at 115 pJ/info. bit.


Polar codes Successive-cancellation decoding 



This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC). Claude Thibeault is a member of ReSMiQ. Warren J. Gross is a member of ReSMiQ and SYTACom.


  1. 1.
    Alamdar-Yazdi, A., & Kschischang, F. R. (2011). A simplified successive-cancellation decoder for polar codes. IEEE Communications Letters, 15(12), 1378–1380. doi: 10.1109/LCOMM.2011.101811.111480.CrossRefGoogle Scholar
  2. 2.
    Arıkan, E. (2009). Channel polarization: a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels. IEEE Transactions on Information Theory, 55(7), 3051–3073. doi: 10.1109/TIT.2009.2021379.MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Arıkan, E. (2011). Systematic polar coding. IEEE Communications Letters, 15(8), 860–862. doi: 10.1109/LCOMM.2011.061611.110862.CrossRefGoogle Scholar
  4. 4.
    Balatsoukas-Stimming, A., Karakonstantis, G., & Burg, A. (2014). Enabling complexity-performance trade-offs for successive cancellation decoding of polar codes. In IEEE international symposium on information theory (ISIT). doi: 10.1109/ISIT.2014.6875380 (pp. 2977–2981).
  5. 5.
    Dizdar, O., & Arıkan, E. (2015). A high-throughput energy-efficient implementation of successive-cancellation decoder for polar codes using combinational logic. arXiv:1412.3829.
  6. 6.
    Giard, P., Sarkis, G., Thibeault, C., & Gross, W. (2015). A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs. In IEEE workshop on signal process. Syst. (SiPS). doi: 10.1109/SiPS.2015.7345007 (pp. 1–6).
  7. 7.
    Huang, Z., Diao, C., & Chen, M. (2012). Latency reduced method for modified successive cancellation decoding of polar codes. Electronics Letters, 48(23), 1505–1506. doi: 10.1049/el.2012.2795.CrossRefGoogle Scholar
  8. 8.
    Leroux, C., Tal, I., Vardy, A., & Gross, W. (2011). Hardware architectures for successive cancellation decoding of polar codes. In IEEE international conference on acoustic, speech, and signal process. (ICASSP) (pp. 1665–1668), DOI  10.1109/ICASSP.2011.5946819, (to appear in print).
  9. 9.
    Mori, R., & Tanaka, T. (2009). Performance and construction of polar codes on symmetric binary-input memoryless channels. In IEEE international symposium on information theory (ISIT). doi: 10.1109/ISIT.2009.5205857 (pp. 1496–1500).
  10. 10.
    Pamuk, A., & Arıkan, E. (2013). A two phase successive cancellation decoder architecture for polar codes. In IEEE international symposium on information theory (ISIT). doi: 10.1109/ISIT.2013.6620368 (pp. 1–5).
  11. 11.
    Park, Y. S., Tao, Y., Sun, S., & Zhang, Z. (2014). A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. In Symposium on VLSI circuits dig. of tech. papers. doi: 10.1109/VLSIC.2014.6858413(pp. 1–2).
  12. 12.
    Sarkis, G., Giard, P., Vardy, A., Thibeault, C., & Gross, W. J. (2014). Fast polar decoders: Algorithm and implementation. IEEE Journal on Selected Areas in Communications, 32(5), 946–957. doi: 10.1109/JSAC.2014.140514.CrossRefGoogle Scholar
  13. 13.
    Tal, I., & Vardy, A. (2013). How to construct polar codes. IEEE Transactions on Information Theory, 59 (10), 6562–6582. doi: 10.1109/TIT.2013.2272694.MathSciNetCrossRefzbMATHGoogle Scholar
  14. 14.
    Trifonov, P. (2012). Efficient design and decoding of polar codes. IEEE Transactions on Communications, 60 (11), 3221–3227. doi: 10.1109/TCOMM.2012.081512.110872.CrossRefGoogle Scholar
  15. 15.
    Yuan, B., & Parhi, K. (2014). Low-latency successive-cancellation polar decoder architectures using 2-bit decoding. IEEE Transactions on Circuits and Systems I, 61(4), 1241–1254. doi: 10.1109/TCSI.2013.2283779.CrossRefGoogle Scholar
  16. 16.
    Zhang, L., Zhang, Z., Wang, X., Zhong, C., & Ping, L. (2015). Simplified successive-cancellation decoding using information set reselection for polar codes with arbitrary blocklength. IET Communications, 9(11), 1380–1387. doi: 10.1049/iet-com.2014.0988.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringMcGill UniversityMontréalCanada
  2. 2.Telecommunications Circuits LaboratoryÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  3. 3.Department of Electrical EngineeringÉcole de Technologie SupérieureMontréalCanada

Personalised recommendations