Low-Latency Software Polar Decoders
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Polar codes are a new class of capacity-achieving error-correcting codes with low encoding and decoding complexity. Their low-complexity decoding algorithms rendering them attractive for use in software-defined radio applications where computational resources are limited. In this work, we present low-latency software polar decoders that exploit modern processor capabilities. We show how adapting the algorithm at various levels can lead to significant improvements in latency and throughput, yielding polar decoders that are suitable for high-performance software-defined radio applications on modern desktop processors and embedded-platform processors. These proposed decoders have an order of magnitude lower latency and memory footprint compared to state-of-the-art decoders, while maintaining comparable throughput. In addition, we present strategies and results for implementing polar decoders on graphical processing units. Finally, we show that the energy efficiency of the proposed decoders is comparable to state-of-the-art software polar decoders.
KeywordsPolar codes Successive-cancellation decoding Software decoders
The authors wish to thank Samuel Gagné of École de technologie supérieure and CMC Microsystems for providing access to the Intel Core i7-4770S processor and NVIDIA Tesla K20c graphical processing unit, respectively. Claude Thibeault is a member of ReSMiQ. Warren J. Gross is a member of ReSMiQ and SYTACom.
- 1.PCI (2006). Express base specification revision 2.0. PCI-SIG.Google Scholar
- 2.IEEE (2008). Standard for floating-point arithmetic. IEEE Std 754–2008 pp. 1–70. doi: 10.1109/IEEESTD.2008.4610935.
- 3.IEEE (2012). Standard for information technology–telecommunications and information exchange between systems local and metropolitan area networks–specific requirements part 11: wireless LAN medium access control (MAC) and physical layer (PHY) specifications. IEEE Std 802.11-2012 (Revision of IEEE Std 802.11–2007), 1–2793. doi: 10.1109/IEEESTD.2012.6178212.
- 9.Giard, P., Sarkis, G., Thibeault, C., & Gross, W. J. (2014). Fast software polar decoders. In IEEE international conference on acoustic, speech, and signal process. (ICASSP). doi: 10.1109/ICASSP.2014.6855069 (pp. 7555–7559).
- 10.Han, X., Niu, K., & He, Z. (2013). Implementation of IEEE 802.11n LDPC codes based on general purpose processors. In IEEE international conference on communication technology. (ICCT). doi: 10.1109/ICCT.2013.6820375 (pp. 218–222).
- 13.Le Gal, B., Leroux, C., & Jego, C. (2014). Software polar decoder on an embedded processor. In IEEE international workshop on signal processing system. (SiPS). doi: 10.1109/SiPS.2014.6986083.
- 16.NVIDIA (2012). Kepler GK110 - the fastest, most efficient HPC architecture ever built. NVIDIA’s Next Generation CUDA Computer Architecture: Kepler GK110.Google Scholar
- 17.NVIDIA (2014). NVIDIA management library (NVML), NVML API Reference Guide.Google Scholar
- 18.NVIDIA (2014). Performance guidelines. CUDA C Programming Guide.Google Scholar
- 19.Sarkis, G., Giard, P., Thibeault, C., & Gross, W.J. (2014). Autogenerating software polar decoders. In IEEE global conference on signal and information processing. (GlobalSIP). doi: 10.1109/GlobalSIP.2014.7032067 (pp. 6–10).
- 24.Treibig, J., Hager, G., & Wellein, G. (2010). LIKWID: A lightweight performance-oriented tool suite for x86 multicore environments. In International conference on parallel process. Workshops (ICPPW). doi: 10.1109/ICPPW.2010.38 (pp. 207–216).
- 25.Wang, G., Wu, M., Yin, B., & Cavallaro, J. R. (2013). High throughput low latency LDPC decoding on GPU for SDR systems. In IEEE global conference on signal and information processing. (GlobalSIP). doi: 10.1109/GlobalSIP.2013.6737137 (pp. 1258–1261).
- 26.Xianjun, J., Canfeng, C., Jaaskelainen, P., Guzma, V., & Berg, H. (2013). A 122 Mb/s turbo decoder using a mid-range GPU. In International wireless communication and mobile comput. Conference. (IWCMC). doi: 10.1109/IWCMC.2013.6583709 (pp. 1090–1094).