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A Hardware-Efficient Method for Extracting Statistic Information of Connected Component

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Abstract

The statistic information of connected components are fundamental for image processing, which could be acquired through connected components labeling. This paper proposes a hardware-efficient method for extracting statistic information of connected components in a binary image to accelerate image processing in embedded application. The proposed method scans two adjacent rows with 2 × 2 template simultaneously, meanwhile, statistic information of runs are recorded. After scanning two rows, the equivalent runs are merged, and then statistic information of completed connected region is exported directly. This method scans an image only once, which could reduce off-chip memory access massively. For a determined image resolution, the requirement of on-chip memory resource is also confirmed and not affected by the number of connected components. This algorithm is modeled with Verilog, and the simulation result shows that average processing speed could be real-time for various images with different resolution. Furthermore, the memory cost is little compared to other hardware based algorithms for labeling connected components, and the proposed method is appropriated for hardware implementation.

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References

  1. 1.

    Amir, A., Zimet, L., Sangiovanni-Vincentelli, A., & Kao, S. (2005). An embedded system for an eye-detection sensor. Computer Vision and Image Understanding, 98(1), 104–123. doi:10.1016/j.cviu.2004.07.009.

  2. 2.

    Hedberg, H., Kristensen, F., & Owall, V. (2007). Implementation of a labeling algorithm based on contour tracing with feature extraction. IEEE International Symposium on Circuits and Systems, 1101–1104, doi:10.1109/ISCAS.2007.378202.

  3. 3.

    Rosenfeld, A. (1966). Sequential operations in digital picture processing. Journal of the ACM, 13(4), 471–494. doi:10.1145/321356.321357.

  4. 4.

    Samet, H., & Tamminen, M. (1986). An improved approach to connected component labeling of images. Paper presented at the Proc. Int. Conf. Comput. Vision Pattern Recog.

  5. 5.

    Lumia, R., Shapiro, L. G., & Zuniga, O. A. (1983). A new connected components algorithm for virtual memory computers. Computer Vision, Graphics, and Image Processing, 22(2), 287–300.

  6. 6.

    Fiorio, C., & Gustedt, J. (1996). Two linear time union-find strategies for image processing. Theoretical Computer Science, 154, 165–181.

  7. 7.

    Lifeng, H., Yuyan, C., & Suzuki, K. A linear-time two-scan labeling algorithm. In Image Processing, 2007. ICIP 2007. IEEE International Conference on, Sept. 16 2007-Oct. 19 2007 2007 (Vol. 5, pp. V - 241-V - 244). doi:10.1109/ICIP.2007.4379810.

  8. 8.

    He, L., Chao, Y., & Suzuki, K. (2008). A run-based two-scan labeling algorithm. IEEE Transactions on Image Processing, 17(5). doi: 10.1605/01.301-0014173920.2011.

  9. 9.

    He, L., Chao, Y., & Suzuki, K. (2009). Fast connected-component labeling. Pattern Recognition, 42(9), 1977–1987. doi:10.1016/j.patcog.2008.10.013.

  10. 10.

    Grana, C., Borghesani, D., & Cucchiara, R. (2010). Optimized block-based connected components labeling with decision trees. IEEE Transactions on Image Processing, 19(6), 1596–1609.

  11. 11.

    Suzuki, K., Horiba, I., & Sugie, N. (2003). Linear-time connected-component labeling based on sequential local operations. Computer Vision and Image Understanding, 89(1), 1–23. doi:10.1016/S1077-3142(02)00030-9.

  12. 12.

    Fiorio, C., & Gustedt, J. (2005). Optimizing connected component labeling algorithms. Paper presented at the Proc. SPIE Conf. Med. Imag.

  13. 13.

    Fu, C., & Chun-Jen, C. A component-labeling algorithm using contour tracing technique. In Document Analysis and Recognition, 2003. Proceedings. Seventh International Conference on, 3-6 Aug. 2003 2003 (pp. 741–745). doi:10.1109/ICDAR.2003.1227760.

  14. 14.

    Kruse, B. (1980). A fast algorithm for segmentation of connected components in binary images. Paper presented at the Proc. 1st Scandinavian Conf. Image Anal., Lund, Sweden, Jan.

  15. 15.

    Danielsson, P.-E. (1981). An improvement of Kruse’s segmentation algorithm. Computer Graphics and Image Processing, 17(4), 394–396.

  16. 16.

    Bailey, D. G., & Johnston, C. T. (2007). Single pass connected components analysis. Paper presented at the Image and Vision Computing New Zealand.

  17. 17.

    Johnston, C. T., & Bailey, D. G. FPGA implementation of a single pass connected components algorithm. In Electronic design, test and applications, 2008. DELTA 2008. 4th IEEE International Symposium on, 23-25 Jan. 2008 2008 (pp. 228–231). doi:10.1109/DELTA.2008.21.

  18. 18.

    Kumar, V. S., Irick, K., Al Maashri, A., & Vijaykrishnan, N. A scalable bandwidth aware architecture for connected component labeling. In VLSI (ISVLSI), 2010 I.E. Computer Society Annual Symposium on, 5-7 July 2010 2010 (pp. 116–121). doi:10.1109/ISVLSI.2010.89.

  19. 19.

    Chung-Yuan, L., Sz-Yan, L., & Tsung-Han, T. A scalable parallel hardware architecture for connected component labeling. In Image Processing (ICIP), 2010 17th IEEE International Conference on, 26-29 Sept. 2010 2010 (pp. 3753–3756). doi:10.1109/ICIP.2010.5653457.

  20. 20.

    Shyue-Wen, Y., Ming-hwa, S., Hsien-Huang, W., Hung-En, C., Ping-Kuo, W., & Ying-Yih, W. VLSI architecture design for a fast parallel label assignment in binary image. In Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 23-26 May 2005 2005 (pp. 2393–2396 Vol. 2393). doi:10.1109/ISCAS.2005.1465107.

  21. 21.

    Zhao, C., Mei, K., & Zheng, N. (2014). Design of write merging and read prefetching buffer in DRAM controller for embedded processor. Microprocessors and Microsystems, 38(5), 451–457. doi:10.1016/j.micpro.2014.03.010.

  22. 22.

    Appiah, K., Hunter, A., Dickinson, P., & Owens, J. A run-length based connected component algorithm for FPGA implementation. In ICECE Technology, 2008. FPT 2008. International Conference on, 8-10 Dec. 2008 2008 (pp. 177–184). doi:10.1109/FPT.2008.4762381.

  23. 23.

    Flatt, H., Blume, S., Hesselbarth, S., Schunemann, T., & Pirsch, P. A parallel hardware architecture for connected component labeling based on fast label merging. In Application-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on, 2-4 July 2008 2008 (pp. 144–149). doi:10.1109/ASAP.2008.4580169.

  24. 24.

    In-Yong, J., & Chang-Sung, J. Parallel connected-component labeling algorithm for GPGPU applications. In Communications and Information Technologies (ISCIT), 2010 International Symposium on, 26-29 Oct. 2010 2010 (pp. 1149–1153). doi:10.1109/ISCIT.2010.5665161.

  25. 25.

    Chen, P., Zhao, H. L., Tao, C., & Sang, H. S. (2011). Block-run-based connected component labelling algorithm for GPGPU using shared memory. Electronics Letters, 47(24), 1309–1311. doi:10.1049/el.2011.2941.

  26. 26.

    The USC-SIPI Image Database. http://sipi.usc.edu/database.

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Acknowledgments

This work is supported by National Natural Science Foundation of China (grant number is 61231018).

Author information

Correspondence to Chen Zhao.

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Funding

This study was funded by National Natural Science Foundation of China (grant number is 61231018).

Conflict of Interest

The authors declare that they have no conflict of interest.

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Zhao, C., Duan, G. & Zheng, N. A Hardware-Efficient Method for Extracting Statistic Information of Connected Component. J Sign Process Syst 88, 55–65 (2017). https://doi.org/10.1007/s11265-016-1126-5

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Keywords

  • Connected component
  • Extracting statistic information
  • Hardware implementation