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Journal of Signal Processing Systems

, Volume 82, Issue 3, pp 311–329 | Cite as

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design

  • Carlo SauEmail author
  • Nicola Carta
  • Luigi Raffo
  • Francesca Palumbo
Article
  • 232 Downloads

Abstract

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology.

Keywords

Signal processing Dataflow MoC MPEG-RVC Coarse-grained reconfigurability Low-power Clock gating 

Notes

Acknowledgments

Prof. Luigi Raffo and Dr. Carlo Sau are grateful to Sardinia Regional Government for funding the RPCT Project (L.R. 7/2007, CRP-18324) that led to these results. Dr. Sau is also grateful to Sardinia Regional Government for supporting his PhD scholarship (P.O.R. F.S.E., European Social Fund 2007-2013 - Axis IV Human Resources).

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Carlo Sau
    • 1
    Email author
  • Nicola Carta
    • 1
  • Luigi Raffo
    • 1
  • Francesca Palumbo
    • 2
  1. 1.DIEE Department of Electrical and Electronic Engineering EOLAB-Microelectronics and Bioengineering LabUniversity of Cagliari (IT)CagliariItaly
  2. 2.PolComIng Information Engineering UnitUniversity of Sassari (IT)SassariItaly

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