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Journal of Signal Processing Systems

, Volume 83, Issue 3, pp 357–371 | Cite as

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

  • Davide ZoniEmail author
  • Federico Terraneo
  • William Fornaciari
Article

Abstract

Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. On-chip network affects also the overall power consumption, thus requiring accurate early-stage estimation and optimization methodologies. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS) technique have been proposed both for CPUs and NoCs. The promise is to be a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, a reliable full system analysis requires to integrate in the toolchain accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator overheads are considered at the same time. This work proposes a complete cycle accurate framework for multi-core design supporting Global Asynchronous Local Synchronous (GALS) NoC design and DVFS actuators for the NoC. Furthermore, static and dynamic frequency assignment is possible with or without the use of the voltage regulator. The proposed framework sits on accurate analytical timing model and SPICE-based power measures, providing accurate estimates of both timing and power overheads of the power control mechanisms.

Keywords

Network-on-Chip Simulation DVFS GALS Simulation Multi-cores 

References

  1. 1.
    Ogras, U., Marculescu, R., Choudhary, P., & Marculescu, D. (2007). Voltage-frequency island partitioning for gals-based networks-on-chip. In: Design Automation Conference, 2007. DAC ’07. 44th ACM/IEEE. (pp. 110–115).Google Scholar
  2. 2.
    Chapiro, D. M. (1984). Globally-asynchronous locally-synchronous systems, Ph.D. dissertation, Stanford University, Report No. STAN-CS-84-1026.Google Scholar
  3. 3.
    Mishra, A. K., Yanamandra, A., Das, R., Eachempati, S., Iyer, R., Vijaykrishnan, N., & Das, C. R. (2011). Raft: A router architecture with frequency tuning for on-chip networks. J. Parallel Distrib. Comput., 71 (5), 625–640. [Online]. Available: doi: 10.1016/j.jpdc.2010.09.005.
  4. 4.
    Renau, J., Fraguela, B., Tuck, J., Liu, W., Prvulovic, M., Ceze, L., Sarangi, S., Sack, P., Strauss, K., & Montesinos, P. (2005). SESC simulator. In: http://sesc.sourceforge.net.
  5. 5.
    Soteriou, V., Eisley, N., Wang, H., Li, B., & Peh, L.-S. (2006). Polaris: A system-level roadmap for on-chip interconnection networks. In: ICCD 2006., pp.134 –141.Google Scholar
  6. 6.
    Hsieh, M.-y., Rodrigues, A., Riesen, R., Thompson, K., & Song, W. (2011). A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration. SIGMETRICS Perform. Eval. Rev., 38, 63–68.CrossRefGoogle Scholar
  7. 7.
    Lis, M., Ren, P., Cho, M. H., Shim, K. S., Fletcher, C., Khan, O., & Devadas, S. (2011). Scalable, accurate multicore simulation in the 1000-core era. In: Performance Analysis of Systems and Software (ISPASS), IEEE International Symposium on (pp. 175 –185).Google Scholar
  8. 8.
    Bartolini, A., Cacciari, M., Tilli, A., Benini, L., & Gries, M. (2010). A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. In: GLSVLSI’10. New York, NY, USA: ACM, pp. 311–316.Google Scholar
  9. 9.
    Zoni, D., Corbetta, S., & Fornaciari, W. (2012). Hands: Heterogeneous architectures and networks-on-chip design and simulation. In: IEEE ISLPED’12, aug.Google Scholar
  10. 10.
    Corbetta, S., Zoni, D., & Fornaciari, W. (2012). A temperature and reliability oriented simulation framework for multi-core architectures. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI2012), University of Massachusetts, Amherst. USA.Google Scholar
  11. 11.
    Carlson, T., Heirman, W., & Eeckhout, L. (2011). Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation,” in. In: High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for (pp. 1–12).Google Scholar
  12. 12.
    Prabhu, S., Grot, B., Gratz, P. V., & Hu, J. (2009). Ocin tsim- dvfs aware simulator for nocs.Google Scholar
  13. 13.
    Peh, L.-S., & Dally, W. J. A delay model for router microarchitectures. IEEE Micro, 21(1), 26–34. Jan. 2001. [Online]. Available: doi: 10.1109/40.903059
  14. 14.
    Zoni, D., Terraneo, F., & Fornaciari, W. Source code.” [Online]. Available: http://hipeaclab.deib.polimi.it.
  15. 15.
    Terraneo, F., Zoni, D., & Fornaciari, W. (2013). A cycle accurate simulation framework for asynchronous noc design. In: System on Chip (SoC), International Symposium on, Oct 2013.Google Scholar
  16. 16.
  17. 17.
    Alhussien, A., Wang, C., & Bagherzadeh, N. (2010). A scalable delay insensitive asynchronous noc with adaptive routing. In: Telecommunications (ICT), 2010 IEEE 17th International Conference on (pp. 995–1002).Google Scholar
  18. 18.
    Panades, M. I., & Greiner, A. (2007). Bi-synchronous fifo for synchronous circuit communication well suited for network-on-chip in gals architectures. In: Networks-on-Chip, 2007. NOCS 2007. First International Symposium on. (pp. 83–94).Google Scholar
  19. 19.
    Brooks, D., Tiwari, V., & Martonosi, M. (2000). Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th annual international symposium on Computer architecture, ser. ISCA ’00. New York, NY, USA: ACM (pp. 83–94).Google Scholar
  20. 20.
    Beigne, E., Clermidy, F., Miermont, S., & Vivet, P. (2008). Dynamic voltage and frequency scaling architecture for units integration within a gals noc. In: Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on (pp. 129–138).Google Scholar
  21. 21.
    Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., & Wood, D. A. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2), 1–7. Aug. 2011. [Online]. Available: doi: 10.1145/2024716.2024718.
  22. 22.
    Agarwal, N., Krishna, T., Peh, L.-S., & Jha, N. (2009). Garnet: A detailed on-chip network model inside a full-system simulator. In: ISPASS.Google Scholar
  23. 23.
    Zhao, W., & Cao, Y. (2006). New generation of predictive technology model for sub-45nm design exploration. In: Quality Electronic Design, ISQED ’06. 7th International Symposium on, pp. 6 pp. –590.Google Scholar
  24. 24.
    Butcher, J. C. Numerical methods for ordinary differential equations. In: J. Wiley, 2003. [Online]. Available: http://www.worldcat.org/isbn/9780471967583.
  25. 25.
    Duarte, D. E. (2002). Clock network and phase-locked loop power estimation and experimentation: Ph.D. dissertation, Pennsylvania State University.Google Scholar
  26. 26.
    Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.-C., Brown, J., & Agarwal, A. (2007). On-chip interconnection architecture of the tile processor. In: Micro.Google Scholar
  27. 27.
    Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., & Brown, R. B. (2001). Mibench: A free, commercially representative embedded benchmark suite. In: Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop. Washington, DC, USA: IEEE Computer Society (pp. 3–14).Google Scholar
  28. 28.
    Keating, M., Flynn, D., Aitken, R., Gibbons, A., & Shi, K. (2007). Low Power Methodology Manual: For System-on-Chip Design. Springer Publishing Company. In: Incorporated.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Davide Zoni
    • 1
    Email author
  • Federico Terraneo
    • 1
  • William Fornaciari
    • 1
  1. 1.Politecnico di Milano - DEIBMilanoItaly

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