Journal of Signal Processing Systems

, Volume 81, Issue 3, pp 411–424 | Cite as

3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation

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Abstract

This paper presents a Field Programmable Gate Array (FPGA) based embedded system which is used to achieve high speed segmentation of 3D images. Segmentation is performed using Expectation-Maximization (EM) with Maximization of Posterior Marginals (MPM) Bayesian algorithm. This algorithm segments the 3D image using neighboring pixels based on a Markov Random Field (MRF) model. In this system, the embedded processor controls a custom circuit which performs the MPM and portions of the EM algorithm. The embedded processor completes the EM algorithm and also controls image data transmission between host computer and on-board memory. The whole system has been implemented on Xilinx Virtex 6 FPGA and achieved over 100 times processing improvement compared to standard desktop computer. Three new techniques were the key to achieve this speed: Pipelined computational cores, sixteen parallel data paths and a novel memory interface for maximizing the external memory bandwidth.

Keywords

3D image segmentation EM/MPM FPGA 
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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  1. 1.Indiana University Purdue University at IndianapolisIndianapolisUSA

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