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Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

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Abstract

Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design low-power multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platform clocked at 1Ghz, which is an improvement of more than 100 % over previously proposed implementations.

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Author information

Correspondence to Hervé Yviquel.

Additional information

We would like to thank the organizations which have partially funded this work such as the Center for International Mobility (CIMO) and the Academy of Finland (funding decision 253087). We would also give special thanks to the Orcc and TCE communities as a whole for actively participating in the development of the tools which offers solid basements to this work.

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Yviquel, H., Sanchez, A., Jääskeläinen, P. et al. Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. J Sign Process Syst 80, 121–136 (2015). https://doi.org/10.1007/s11265-014-0953-5

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Keywords

  • Dataflow programming
  • Video coding
  • HEVC
  • Embedded system