Journal of Signal Processing Systems

, Volume 80, Issue 1, pp 49–64 | Cite as

Code Density and Energy Efficiency of Exposed Datapath Architectures

  • Pekka Jääskeläinen
  • Heikki Kultala
  • Timo Viitanen
  • Jarmo Takala


Exposing details of the processor datapath to the programmer is motivated by improvements in the energy efficiency and the simplification of the microarchitecture. However, an instruction format that can control the data path in a more explicit manner requires more expressiveness when compared to an instruction format that implements more of the control logic in the processor hardware and presents conventional general purpose register based instructions to the programmer. That is, programs for exposed datapath processors might require additional instruction memory bits to be fetched, which consumes additional energy. With the interest in energy and power efficiency rising in the past decade, exposed datapath architectures have received renewed attention. Several variations of the additional details to expose to the programmer have been proposed in the academy, and some exposed datapath features have also appeared in commercial architectures. The different variations of proposed exposed datapath architectures and their effects to the energy efficiency, however, have not so far been analyzed in a systematic manner in public. This article provides a review of exposed datapath approaches and highlights their differences. In addition, a set of interesting exposed datapath design choices is evaluated in a closer study. Due to the fact that memories constitute a major component of power consumption in contemporary processors, we analyze instruction encodings for different exposed datapath variations and consider the energy required to fetch the additional instruction bits in comparison to the register file access savings achieved with the exposed datapath.


Processor architectures Exposed datapath architectures Software bypassing Low power computing VLIW TTA 



This work was funded by Academy of Finland (funding decision 253087), Finnish Funding Agency for Technology and Innovation (project ”Parallel Acceleration”, funding decision 40115/13), and ARTEMIS Joint Undertaking under grant agreement no 641439 (ALMARVI).


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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Pekka Jääskeläinen
    • 1
  • Heikki Kultala
    • 1
  • Timo Viitanen
    • 1
  • Jarmo Takala
    • 1
  1. 1.Tampere University of TechnologyTampereFinland

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