Journal of Signal Processing Systems

, Volume 76, Issue 3, pp 249–259 | Cite as

A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS

Article

Abstract

Modular arithmetic is a building block for a variety of applications potentially supported on embedded systems. An approach to turn modular arithmetic more efficient is to identify algorithmic modifications that would enhance the parallelization of the target arithmetic in order to exploit the properties of parallel devices and platforms. The Residue Number System (RNS) introduces data-level parallelism, enabling the parallelization even for algorithms based on modular arithmetic with several data dependencies. However, the mapping of generic algorithms to full RNS-based implementations can be complex and the utilization of suitable hardware architectures that are scalable and adaptable to different demands is required. This paper proposes and discusses an architecture with scalability features for the parallel implementation of algorithms relying on modular arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular arithmetic algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular arithmetic algorithms. An implementation with the Xilinx Virtex 4 and Altera Stratix II Field Programmable Gate Array (FPGA) technologies of the modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and (EC) cryptographic algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.

Keywords

Residue number system (RNS) Modular arithmetic Cryptography Embedded systems Electronic design automation (EDA) 

Notes

Acknowledgments

This work was supported by national funds through FCT - Fundação para a Ciência e Tecnologia, under the project PEst-OE/EEI/LA0021/2013.

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Signal Processing Systems GroupINESC-IDLisbonPortugal
  2. 2.Department of Electrical and Computer Engineering, Instituto Superior TécnicoUniversidade de LisboaLisbonPortugal

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