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Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation

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When the code length is moderate, non-binary low-density parity-check (NB-LDPC) codes can achieve better error correcting performance than their binary counterparts at the expense of higher decoding complexity. The check node processing is a major bottleneck of NB-LDPC decoding. This paper proposes novel schemes for both the Min-max and the simplified Min-sum check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs based on the Min-max algorithm with forward-backward scheme, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over G F(32), the proposed scheme reduces the CNU area by at least 32 %, and leads to higher clock frequency. Compared to the prior simplified Min-sum based design, the proposed CNU is more regular, and can achieve good throughput-area tradeoff.

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This material is based upon work supported by the National Science Foundation under Grant No.0846331.

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Correspondence to Fang Cai.

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Cai, F., Zhang, X. Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. J Sign Process Syst 76, 211–222 (2014).

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  • Non-binary LDPC decoding
  • Power representation
  • VLSI
  • Check node unit architecture
  • Min-max algorithm
  • Simplified Min-sum algorithm