This paper presents a new multi-core platform that can decode various video compression formats including MPEG-2, MPEG-4, AVS, and H.264/AVC. The developed multi-core platform consists of multiple media cores that are designed based on an application-specific instruction-set processor (ASIP). To improve the decoding speed of each media core, we developed several designated instructions that are useful for decoding various video codecs. In addition, an inter-connected hardware structure and a new synchronization algorithm are proposed to reduce inter-core communication overheads and a shared memory contention on the multi-core platform. We achieved a speed-up of 2.2× in decoding video bitstreams using several designated instructions on the media core. Furthermore, we achieved a speed-up of 5.56× in decoding video bitstreams on the multi-core platform by employing macroblock-row level parallelism, compared with the developed media core without designated instructions. The developed multi-core platform was implemented on a Xilinx Virtex5 LX330 field-programmable gate array (FPGA) that operates at 60 MHz.
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This work was partly supported by the IT R&D program of MSIP/KEIT [10042395, Development of SW emulation and rapid prototyping technology for high-performance SoC based-on multi-core] and partly supported by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the C-ITRC (Convergence Information Technology Research Center) support program (NIPA-2013-H0301-13-1006) supervised by the NIPA (National IT Industry Promotion Agency) and the Research Grant of Kwangwoon University in 2013.
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Jo, H., Ahn, Y., Kang, D. et al. Flexible Multi-Core Platform for a Multiple-Format Video Decoder. J Sign Process Syst 80, 163–179 (2015). https://doi.org/10.1007/s11265-013-0853-0
- Video decoder
- Multi-core platform