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Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m)

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Abstract

In this paper, the design and circuit implementation of a polynomial basis multiplier architecture over Galois Fields GF(2m) is presented. The proposed architecture supports field multiplication of two m-term polynomials where m is a positive integer. Circuit implementations based on this parameterized architecture where m is configurable is suitable for applications in error control coding and cryptography. The proposed architecture offers low latency, polynomial basis multiplication where the irreducible polynomial P(x) = x m + p kt . x kt + … + p 1. x + 1 with mkt + 4 is dynamically reconfigurable. Results of the complexity analysis show that the proposed architecture requires less logic resources compared to existing sequential polynomial basis multipliers. In terms of timing performance, the proposed architecture has a latency of m/4, which is the lowest among the multipliers found in literature for GF(2m).

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Correspondence to Huong Ho.

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Ho, H. Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m). J Sign Process Syst 75, 203–208 (2014). https://doi.org/10.1007/s11265-013-0791-x

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Keywords

  • Finite fields
  • Polynomial basis
  • Parameterized
  • Low latency
  • Hardware implementations