Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard

  • 438 Accesses

  • 4 Citations


Video encoding and decoding are computing intensive applications that require high performance processors or dedicated hardware. Video decoding offers a high parallel processing potential that may be exploited. However, a particular task challenges parallelization: entropy decoding. In H.264 and SVC video standards, this task is mainly carried out using arithmetic decoding, an strictly sequential algorithm that achieves results close to the entropy limit. By accelerating arithmetic decoding, the bottleneck is removed and parallel decoding is enabled. Many works have been published on accelerating pure binary encoding and decoding. However, little research has been done into how to integrate binary decoding with context managing and control without losing performance. In this work we propose a FPGA-based architecture that achieves real time decoding for high-definition video by sustaining a 1 bin per cycle throughput. This is accomplished by implementing fast bin decoding; a novel and area efficient context-managing mechanism; and optimized control scheduling.

This is a preview of subscription content, log in to check access.

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15


  1. 1.

    Azevedo, A., Juurlink, B., Meenderinck, C., Terechko, A., Hoogerbrugge, J., Alvarez, M., Ramirez, A., Valero, M. (2009). A highly scalable parallel implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers (HiPEAC), 4(2), 1–25.

  2. 2.

    Chen, J.W., & Lin, Y.L. (2009). A high-performance hardwired CABAC decoder for ultra-high resolution video. IEEE Transactions on Consumer Electronics, 55(3), 1614–1622.

  3. 3.

    Patterson, D. A., et al. (2006). The landscape of parallel computing research: a view from Berkeley. Tech. rep.

  4. 4.

    Eeckhaut, H., Christiaens, M., Stroobandt, D., Nollet, V. (2006). Optimizing the critical loop in the H.264/AVC CABAC decoder. In FPT (pp. 113–118).

  5. 5.

    FFmpeg: http://ffmpeg.mplayerhq.hu. Accessed September 2012.

  6. 6.

    Hong, Y., Liu, P., Zhang, H., You, Z., Zhou, D., Goto, S. (2009). A 360 mbin/s CABAC decoder for H.264/AVC level 5.1 applications. In Proc. ISOCC (pp. 71–74).

  7. 7.

    Kuon, I., & Rose, J. (2007). Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2), 203–215.

  8. 8.

    Li, L., Song, Y., Li, S., Ikenaga, T., Goto, S. (2008). A hardware architecture of CABAC encoding and decoding with dynamic pipeline for H.264/AVC. Journal of Signal Processing System, 50, 81–95.

  9. 9.

    Liao, Y.H., Li, G.L., Chang, T.S. (2010). A high throughput vlsi design with hybrid memory architecture for H.264/AVC CABAC decoder. In Proceedings of ISCAS (pp. 2007–2010).

  10. 10.

    Lin P. C., Chuang T. D., Chen L. G.(2009). A branch selection multi-symbol high throughput CABAC decoder architecture for H.264/AVC. In Proceedings of ISCAS (pp. 365–368).

  11. 11.

    Marpe, D., Schwartz, H., Wiegand, T. (2003). Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 620–636.

  12. 12.

    Osorio, R., & Bruguera, J. (2008). An FPGA architecture for CABAC decoding in manycore systems. In Proceedings of ASAP (pp. 293–298).

  13. 13.

    Själander, M., Terechko, A., Duranton, M. (2008). A look-ahead task management unit for embedded multi-core architectures. In Proceedings of DSD (pp. 149–157).

  14. 14.

    Son, W., & Park, I. (2008). Prediction-based real-time CABAC decoder for high definition H.264/AVC. In ISCAS (pp. 33–36).

  15. 15.

    Wiegand, T., Sullivan, G.J., Bjøntegaard, G., Luthra, A. (2003). Overview of the H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560–576.

  16. 16.

    Xilinx: Virtex 4. http://www.xilinx.com/products/silicon-devices/fpga/index.htm. Accessed September 2012.

  17. 17.

    Xu, M., Cheng, Y., Ran, F., Chen, Z. (2007). Optimizing design and FPGA implementation for CABAC decoder. In Proceedings of HDP (pp. 1–5).

  18. 18.

    Yang, Y. C., & Guo, J. I. (2009). High-throughput H.264/AVC High-Profile CABAC decoder for HDTV applications. IEEE Transactions on Circuits and Systems for Video Technology, 19(9), 1395–1399.

  19. 19.

    Yi, Y., & Park, I. (2007). High speed H.264/AVC CABAC decoding. IEEE Transactions on Circuits and Systems for Video Technology, 17(4), 490–494.

  20. 20.

    Yu, W., & He, Y. (2005). A high performance CABAC decoding architecture. IEEE Transactions on Consumer Electronics, 51(4), 1352–1359.

  21. 21.

    Zhang, P., Xie, D., Gao, W. (2009). Variable-bin-rate CABAC engine for H.264/AVC high definition real-time decoding. IEEE Transactions on Very Large Scale Integration Systems, 17, 417–426.

Download references

Author information

Correspondence to Roberto R. Osorio.

Additional information

Work supported in part by Ministry of Science and Innovation of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2010-17541, and by the Xunta de Galicia, Program for Consolidation of Competitive Research Groups ref. 2010/6 and 2010/28.

The authors are members of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Osorio, R.R., Bruguera, J.D. High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J Sign Process Syst 72, 119–132 (2013). https://doi.org/10.1007/s11265-012-0718-y

Download citation


  • H.264
  • FPGA
  • Arithmetic codes
  • Video coding