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High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard

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Abstract

Video encoding and decoding are computing intensive applications that require high performance processors or dedicated hardware. Video decoding offers a high parallel processing potential that may be exploited. However, a particular task challenges parallelization: entropy decoding. In H.264 and SVC video standards, this task is mainly carried out using arithmetic decoding, an strictly sequential algorithm that achieves results close to the entropy limit. By accelerating arithmetic decoding, the bottleneck is removed and parallel decoding is enabled. Many works have been published on accelerating pure binary encoding and decoding. However, little research has been done into how to integrate binary decoding with context managing and control without losing performance. In this work we propose a FPGA-based architecture that achieves real time decoding for high-definition video by sustaining a 1 bin per cycle throughput. This is accomplished by implementing fast bin decoding; a novel and area efficient context-managing mechanism; and optimized control scheduling.

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Author information

Correspondence to Roberto R. Osorio.

Additional information

Work supported in part by Ministry of Science and Innovation of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2010-17541, and by the Xunta de Galicia, Program for Consolidation of Competitive Research Groups ref. 2010/6 and 2010/28.

The authors are members of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).

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Osorio, R.R., Bruguera, J.D. High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J Sign Process Syst 72, 119–132 (2013). https://doi.org/10.1007/s11265-012-0718-y

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Keywords

  • H.264
  • CABAC
  • FPGA
  • Arithmetic codes
  • Video coding